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liteeth-wi
Author | SHA1 | Date | |
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c44e94da5d | |||
a13569c2eb | |||
5f589aca37 |
5 changed files with 146 additions and 48 deletions
6
firmware/Cargo.toml
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6
firmware/Cargo.toml
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@ -0,0 +1,6 @@
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[package]
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name = "firmware"
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version = "0.1.0"
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edition = "2021"
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[dependencies]
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3
firmware/src/main.rs
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3
firmware/src/main.rs
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@ -0,0 +1,3 @@
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fn main() {
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println!("Hello, world!");
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}
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@ -27,7 +27,7 @@ from liteeth.common import *
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from liteeth import phy as liteeth_phys
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from liteeth.mac import LiteEthMAC
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from liteeth.core import LiteEthUDPIPCore
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from liteeth_cores import LiteEthUDPIPCore
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from liteeth.core.udp import LiteEthUDP
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# IOs ----------------------------------------------------------------------------------------------
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@ -43,6 +43,9 @@ _io = [
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# IP/MAC Address.
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("ip_address", 0, Pins(32)),
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# Interrupt
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("interrupt", 0, Pins(1)),
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# MII PHY Pads
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("mii_eth_clocks", 0,
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Subsignal("tx", Pins(1)),
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@ -180,40 +183,26 @@ class UDPCore(PHYCore):
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clk_freq=CLK_FREQ,
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dw=8,
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with_sys_datapath=False,
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hybrid=True,
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)
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# DHCP port
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data_width = 32
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# CPU port
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nrxslots = self.core.mac.rx_slots.constant
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ntxslots = self.core.mac.tx_slots.constant
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platform.add_extension(get_udp_streamer_port_ios(
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"dhcp",
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data_width=data_width,
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))
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dhcp_ios = platform.request("dhcp")
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wb_bus = wishbone.Interface()
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platform.add_extension(wb_bus.get_ios("wishbone"))
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self.comb += wb_bus.connect_to_pads(self.platform.request("wishbone"), mode="slave")
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self.add_wb_master(wb_bus)
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dhcp_streamer = LiteEthUDPStreamer(
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self.core.udp,
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ip_address=dhcp_ios.ip_address,
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udp_port=67,
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data_width=data_width,
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tx_fifo_depth=64,
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rx_fifo_depth=64
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ethmac_region_size = (nrxslots + ntxslots)*buffer_depth
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ethmac_region = SoCRegion(
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origin=self.mem_map.get("ethmac", None),
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size=ethmac_region_size,
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cached=False
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)
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self.submodules += dhcp_streamer
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self.comb += [
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# Connect UDP Sink IOs to UDP Steamer.
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dhcp_streamer.sink.valid.eq(dhcp_ios.sink_valid),
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dhcp_streamer.sink.last.eq(dhcp_ios.sink_last),
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dhcp_ios.sink_ready.eq(dhcp_streamer.sink.ready),
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dhcp_streamer.sink.data.eq(dhcp_ios.sink_data),
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# Connect UDP Streamer to UDP Source IOs.
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dhcp_ios.source_valid.eq(dhcp_streamer.source.valid),
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dhcp_ios.source_last.eq(dhcp_streamer.source.last),
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dhcp_streamer.source.ready.eq(dhcp_ios.source_ready),
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dhcp_ios.source_data.eq(dhcp_streamer.source.data),
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]
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self.bus.add_slave(name="ethmac", slave=self.core.mac.bus, region=ethmac_region)
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self.comb += self.platform.request("interrupt").eq(self.core.mac.ev.irq)
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# Pixel port
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data_width = 32
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96
liteeth_cores.py
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96
liteeth_cores.py
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@ -0,0 +1,96 @@
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#
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# This file is part of LiteEth.
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#
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# Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from liteeth.common import *
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from liteeth.mac import LiteEthMAC
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from liteeth.core.arp import LiteEthARP
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from liteeth.core.ip import LiteEthIP
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from liteeth.core.udp import LiteEthUDP
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from liteeth.core.icmp import LiteEthICMP
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# IP Core ------------------------------------------------------------------------------------------
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class LiteEthIPCore(Module, AutoCSR):
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def __init__(self, phy, mac_address, ip_address, clk_freq, dw=8,
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hybrid = False,
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with_icmp = True,
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with_ip_broadcast = True,
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with_sys_datapath = False):
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# Parameters.
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# -----------
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ip_address = convert_ip(ip_address)
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# MAC.
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# ----
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self.submodules.mac = LiteEthMAC(
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phy = phy,
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dw = dw,
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interface = "hybrid" if hybrid else "crossbar",
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with_preamble_crc = True,
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with_sys_datapath = with_sys_datapath,
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)
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# ARP.
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# ----
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self.submodules.arp = LiteEthARP(
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mac = self.mac,
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mac_address = mac_address,
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ip_address = ip_address,
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clk_freq = clk_freq,
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dw = dw,
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)
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# IP.
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# ---
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self.submodules.ip = LiteEthIP(
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mac = self.mac,
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mac_address = mac_address,
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ip_address = ip_address,
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arp_table = self.arp.table,
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with_broadcast = with_ip_broadcast,
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dw = dw,
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)
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# ICMP (Optional).
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# ----------------
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if with_icmp:
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self.submodules.icmp = LiteEthICMP(
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ip = self.ip,
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ip_address = ip_address,
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dw = dw,
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)
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# UDP IP Core --------------------------------------------------------------------------------------
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class LiteEthUDPIPCore(LiteEthIPCore):
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def __init__(self, phy, mac_address, ip_address, clk_freq, dw=8,
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hybrid=False,
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with_icmp = True,
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with_ip_broadcast = True,
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with_sys_datapath = False):
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# Parameters.
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# -----------
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ip_address = convert_ip(ip_address)
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# Core: MAC + ARP + IP + (ICMP).
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# ------------------------------
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LiteEthIPCore.__init__(self,
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phy = phy,
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mac_address = mac_address,
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ip_address = ip_address,
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clk_freq = clk_freq,
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hybrid = hybrid,
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with_icmp = with_icmp,
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dw = dw,
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with_ip_broadcast = with_ip_broadcast,
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with_sys_datapath = with_sys_datapath,
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)
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# UDP.
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# ----
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self.submodules.udp = LiteEthUDP(
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ip = self.ip,
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ip_address = ip_address,
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dw = dw,
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)
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@ -87,18 +87,19 @@ architecture a of arty_a7 is
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ip_address : in std_logic_vector(31 downto 0);
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--== DHCP PORT ==--
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dhcp_ip_address : in std_logic_vector(31 downto 0);
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dhcp_sink_valid : in std_logic;
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dhcp_sink_last : in std_logic;
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dhcp_sink_ready : out std_logic;
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dhcp_sink_data : in std_logic_vector(31 downto 0);
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dhcp_source_valid : out std_logic;
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dhcp_source_last : out std_logic;
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dhcp_source_ready : in std_logic;
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dhcp_source_data : out std_logic_vector(31 downto 0);
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--== WISHBONE PORT ==--
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wishbone_adr : in std_logic_vector(29 downto 0);
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wishbone_dat_w : in std_logic_vector(31 downto 0);
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wishbone_dat_r : out std_logic_vector(31 downto 0);
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wishbone_sel : in std_logic_vector(3 downto 0);
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wishbone_cyc : in std_logic;
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wishbone_stb : in std_logic;
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wishbone_ack : out std_logic;
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wishbone_we : in std_logic;
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wishbone_cti : in std_logic_vector(2 downto 0);
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wishbone_bte : in std_logic_vector(1 downto 0);
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wishbone_err : out std_logic;
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interrupt : out std_logic;
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--== PIXEL DATA PORT ==--
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pixel_bind_port : in std_logic_vector(15 downto 0);
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@ -247,12 +248,15 @@ begin
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ip_address => x"0a141e28", -- 10.20.30.40
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dhcp_ip_address => x"0a141e29", -- 10.20.30.41
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dhcp_sink_valid => '0',
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dhcp_sink_last => '1',
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dhcp_sink_data => x"cafebebe",
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dhcp_source_ready => '1',
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--== WISHBONE PORT ==--
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wishbone_adr => (others => '1'),
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wishbone_dat_w => (others => '1'),
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wishbone_sel => (others => '1'),
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wishbone_cyc => '1',
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wishbone_stb => '1',
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wishbone_we => '1',
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wishbone_cti => (others => '1'),
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wishbone_bte => (others => '1'),
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--== PIXEL DATA PORT ==--
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pixel_bind_port => x"effd", -- port 61437 - "PIXEL"
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