xiretza/splink
1
0
Fork 0
Code Issues Pull requests Projects Releases Wiki Activity

Compare commits

base: xiretza:ea8e6d4b49ccd4667bcdb018421d5fd404079db1
Branches Tags
xiretza:main
xiretza:liteeth-wishbone
..
compare: xiretza:bad48d0e9bc3f7755fba621f08ed606ce74273a1
Branches Tags
xiretza:liteeth-wishbone
xiretza:main

No commits in common. "ea8e6d4b49ccd4667bcdb018421d5fd404079db1" and "bad48d0e9bc3f7755fba621f08ed606ce74273a1" have entirely different histories.
ea8e6d4b49 ... bad48d0e9b

2 changed files with 5 additions and 11 deletions
Show stats Expand all files Collapse all files

14
vhdl/splink.vhdl
View file

@ -40,7 +40,6 @@ architecture a of splink is
signal current_frame: unsigned(31 downto 0);
signal pixels_received: natural range 0 to MAX_STRAND_LEN-1;
signal run : std_logic;
signal clear_write_flags : std_logic;
signal all_strands_written : std_logic;
@ -70,7 +69,6 @@ begin
port map (
n_reset => not reset,
clk => clk,
run => run,
led_addr => led_data_arr(i).addr,
@ -121,12 +119,10 @@ begin
begin
if rising_edge(clk) then
clear_write_flags <= '0';
run <= '0';
if all_strands_written then
frame_number <= current_frame;
clear_write_flags <= '1';
run <= '1';
end if;
if reset then
@ -150,12 +146,10 @@ begin
-- TODO udp_length, range check with MAX_STRAND_LEN
num_pixels <= MAX_STRAND_LEN;
if unsigned(udp_data) >= NUM_STRANDS then
receive_state <= DROP;
else
active_strand <= to_integer(unsigned(udp_data));
receive_state <= FRAME_NUM;
end if;
-- FIXME bounds check
active_strand <= to_integer(unsigned(udp_data));
receive_state <= FRAME_NUM;
when FRAME_NUM =>
if not some_strands_written then

2
vhdl/ws2812_vhdl

@ -1 +1 @@
Subproject commit 0d4146d3a3abeb6a20f9228e61e58f95a71b340a
Subproject commit 0d1688f1840b8b5894b9f4cd027fcc1653dd3657