makefile: make ghdl error on warnings

Makefile.nextpnr

@@ -2,7 +2,7 @@ SYNTH_OUTPUT_FILE = $(SYNTH_WORKDIR)/$(YOSYS_MODULE_NAME).json
 
 $(SYNTH_WORKDIR)/%.json: $(VHDL_FILES) $(VERILOG_FILES) | $(SYNTH_WORKDIR) $(GHDL_WORKDIR)/work-obj$(VHDL_STD).cf
 	$(GHDL) make $(GHDL_FLAGS) $(SYNTH_ENTITY)
-	$(YOSYS) -m $(GHDL_YOSYS_PLUGIN) -l $(SYNTH_WORKDIR)/yosys.log -p 'ghdl $(GHDL_FLAGS) $(SYNTH_ENTITY); read_verilog $(VERILOG_FILES); chformal -remove; synth_xilinx -nodsp -nosrl -flatten -top $*; write_json $@'
+	$(YOSYS) -m $(GHDL_YOSYS_PLUGIN) -l $(SYNTH_WORKDIR)/yosys.log -p 'ghdl $(GHDL_FLAGS) -Werror -Wno-error=binding $(SYNTH_ENTITY); read_verilog $(VERILOG_FILES); chformal -remove; synth_xilinx -nodsp -nosrl -flatten -top $*; write_json $@'
 
 $(SYNTH_WORKDIR)/%.fasm: $(SYNTH_WORKDIR)/%.json $(XDC)
 	$(NEXTPNR) --xdc $(XDC) --json $< --chipdb /usr/share/nextpnr/xilinx-chipdb/$(PART).bin --fasm $@

vhdl/arty_a7.vhdl

@@ -121,6 +121,7 @@ architecture a of arty_a7 is
 	signal pixel_source_src_ip_address : std_logic_vector(31 downto 0);
 	signal pixel_source_src_port : std_logic_vector(15 downto 0);
 
+	signal pixel_source_length : std_logic_vector(15 downto 0);
 	signal pixel_source_valid : std_logic;
 	signal pixel_source_last : std_logic;
 	signal pixel_source_data : std_logic_vector(31 downto 0);
@@ -255,7 +256,7 @@ begin
 		pixel_source_src_ip_address => pixel_source_src_ip_address,
 		pixel_source_src_port => pixel_source_src_port,
 
-		pixel_source_length => open,
+		pixel_source_length => pixel_source_length,
 		pixel_source_valid => pixel_source_valid,
 		pixel_source_last => pixel_source_last,
 		pixel_source_last_be => open,
@@ -343,6 +344,7 @@ begin
 			clk => sys_clk,
 			reset => sys_reset,
 
+			udp_length => pixel_source_length,
 			udp_valid => pixel_source_valid,
 			udp_last => pixel_source_last,
 			udp_data => pixel_source_data_be,

vhdl/splink.vhdl

@@ -11,6 +11,7 @@ entity splink is
 		clk : in std_logic;
 		reset : in std_logic;
 
+		udp_length : in std_logic_vector(15 downto 0);
 		udp_valid : in std_logic;
 		udp_last : in std_logic;
 		udp_data : in std_logic_vector(31 downto 0);
@@ -48,6 +49,8 @@ architecture a of splink is
 
 	-- "PIXL"
 	constant MAGIC_NUMBER : std_logic_vector(31 downto 0) := x"5049584c";
+	-- magic + frame num + strand num (4 bytes each)
+	constant HEADER_LEN : natural := 12;
 
 	type receive_state_t is (MAGIC, FRAME_NUM, STRAND_NUM, DATA, DROP);
 	constant RESET_STATE : receive_state_t := MAGIC;
@@ -140,16 +143,18 @@ begin
 
 				case receive_state is
 					when MAGIC =>
-						if udp_data = MAGIC_NUMBER then
+						if udp_data /= MAGIC_NUMBER then
-							receive_state <= STRAND_NUM;
-						else
 							receive_state <= DROP;
+						else
+							if (unsigned(udp_length) - HEADER_LEN) / 4 > MAX_STRAND_LEN then
+								receive_state <= DROP;
+							else
+								num_pixels <= (to_integer(unsigned(udp_length)) - HEADER_LEN) / 4;
+								receive_state <= STRAND_NUM;
+							end if;
 						end if;
 
 					when STRAND_NUM =>
-						-- TODO udp_length, range check with MAX_STRAND_LEN
-						num_pixels <= MAX_STRAND_LEN;
-
 						if unsigned(udp_data) >= NUM_STRANDS then
 							receive_state <= DROP;
 						else