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base: xiretza:c44e94da5d5cf593d188f638fab37c804f55c642
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xiretza:liteeth-wishbone
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compare: xiretza:a28816b2e622c0ce0fc2c72b93935b3137825add
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xiretza:liteeth-wishbone
xiretza:main

3 commits
c44e94da5d ... a28816b2e6

Author SHA1 Message Date
Xiretza
a28816b2e6 Add patched liteeth.core module to allow hybrid mode 
https://github.com/enjoy-digital/liteeth/pull/116
 2022-07-14 16:04:40 +02:00
Xiretza
67aaf86bcc feat: add blank firmware directory 2022-07-14 15:59:11 +02:00
Xiretza
bbb3ec5d30 Use wishbone interface for CPU port 2022-06-30 18:20:36 +02:00
2 changed files with 4 additions and 16 deletions
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1
.gitignore vendored
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@ -1,3 +1,2 @@
/work/
*.o
__pycache__

19
vhdl/arty_a7.vhdl
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@ -36,7 +36,7 @@ entity arty_a7 is
-- when necessary
pmod_a : out std_logic_vector(7 downto 0);
pmod_b : out std_logic_vector(7 downto 0);
pmod_c : out std_logic_vector(7 downto 0);
pmod_c : in std_logic_vector(7 downto 0);
pmod_d : out std_logic_vector(7 downto 0);
clock_100mhz : in std_logic;
@ -324,20 +324,9 @@ begin
sys_reset <= not pll_locked or not n_reset;
pmod_a <= "00" & drivers(5 downto 0);
pmod_b <= "00" & drivers(11 downto 6);
pmod_c(7) <= '0';
pmod_c(6) <= '0';
pmod_c(5) <= drivers(17);
pmod_c(4) <= drivers(16);
pmod_c(3) <= drivers(15);
pmod_c(2) <= drivers(14);
-- workaround for https://github.com/gatecat/nextpnr-xilinx/issues/42#issuecomment-1183525828
pmod_c(1) <= drivers(12);
pmod_c(0) <= drivers(13);
pmod_d <= "00" & drivers(23 downto 18);
pmod_a <= drivers(7 downto 0);
pmod_b <= drivers(15 downto 8);
pmod_d <= drivers(23 downto 16);
sender: process(sys_clk)
begin