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base: xiretza:bbb3ec5d30c55b59faf993464f6bfb855386a540
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xiretza:main
xiretza:liteeth-wishbone
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compare: xiretza:c2673e35bfcbbfbfad88263bc5a3cf411d4ac427
Branches Tags
xiretza:liteeth-wishbone
xiretza:main

4 commits
bbb3ec5d30 ... c2673e35bf

Author SHA1 Message Date
Xiretza
c2673e35bf gitignore: ignore __pycache__ 2022-07-14 15:57:45 +02:00
Xiretza
327af10b6a fix: workaround nextpnr-xilinx#42 2022-07-14 15:57:45 +02:00
Xiretza
3cbc47eb95 fix: reorganize outputs to 6 strands per PMOD 2022-07-14 15:57:45 +02:00
Xiretza
ed34337a56 feat: add blank firmware directory 2022-07-14 15:57:45 +02:00
4 changed files with 25 additions and 4 deletions
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1
.gitignore vendored
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@ -1,2 +1,3 @@
/work/ /work/
*.o *.o
__pycache__

6
firmware/Cargo.toml Normal file
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@ -0,0 +1,6 @@
[package]
name = "firmware"
version = "0.1.0"
edition = "2021"
[dependencies]

3
firmware/src/main.rs Normal file
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@ -0,0 +1,3 @@
fn main() {
println!("Hello, world!");
}

19
vhdl/arty_a7.vhdl
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@ -36,7 +36,7 @@ entity arty_a7 is
-- when necessary -- when necessary
pmod_a : out std_logic_vector(7 downto 0); pmod_a : out std_logic_vector(7 downto 0);
pmod_b : out std_logic_vector(7 downto 0); pmod_b : out std_logic_vector(7 downto 0);
pmod_c : in std_logic_vector(7 downto 0); pmod_c : out std_logic_vector(7 downto 0);
pmod_d : out std_logic_vector(7 downto 0); pmod_d : out std_logic_vector(7 downto 0);
clock_100mhz : in std_logic; clock_100mhz : in std_logic;
@ -320,9 +320,20 @@ begin
sys_reset <= not pll_locked or not n_reset; sys_reset <= not pll_locked or not n_reset;
pmod_a <= drivers(7 downto 0); pmod_a <= "00" & drivers(5 downto 0);
pmod_b <= drivers(15 downto 8); pmod_b <= "00" & drivers(11 downto 6);
pmod_d <= drivers(23 downto 16);
pmod_c(7) <= '0';
pmod_c(6) <= '0';
pmod_c(5) <= drivers(17);
pmod_c(4) <= drivers(16);
pmod_c(3) <= drivers(15);
pmod_c(2) <= drivers(14);
-- workaround for https://github.com/gatecat/nextpnr-xilinx/issues/42#issuecomment-1183525828
pmod_c(1) <= drivers(12);
pmod_c(0) <= drivers(13);
pmod_d <= "00" & drivers(23 downto 18);
sender: process(sys_clk) sender: process(sys_clk)
begin begin