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xiretza:liteeth-wishbone
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compare: xiretza:0230edd2fb22357d6202bea41f664b9c4634d2dd
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xiretza:liteeth-wishbone
xiretza:main

7 commits
6ff0e77d38 ... 0230edd2fb

Author SHA1 Message Date
Xiretza
0230edd2fb makefile: make ghdl error on warnings 2022-06-06 20:49:53 +02:00
Xiretza
2cc32eb4c2 vhdl: use UDP packet length 2022-06-06 20:38:38 +02:00
Xiretza
ea8e6d4b49 vhdl: only run encoders once all pixels are received 2022-06-06 18:38:56 +02:00
Xiretza
62a06c6bcd Update ws2812 submodule 2022-06-06 18:38:43 +02:00
Xiretza
b97c708148 vhdl: implement bounds checking for strand number 2022-06-06 18:25:27 +02:00
Xiretza
bad48d0e9b vhdl: workaround ghdl#2080 
https://github.com/ghdl/ghdl/issues/2080
 2022-06-06 18:16:31 +02:00
Xiretza
dc31375b55 vhdl: use big-endian network byte order 
liteeth splits the rx data stream into 4-byte chunks and interprets them as
little-endian 32-bit vecs; similar for the other direction.
 2022-06-06 18:13:21 +02:00
1 changed files with 0 additions and 23 deletions
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vhdl/util.vhdl
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@ -1,23 +0,0 @@
library ieee;
use ieee.std_logic_1164.all;
package util is
function flip_endianness(val : in std_logic_vector) return std_logic_vector;
end package;
package body util is
function flip_endianness(val : in std_logic_vector) return std_logic_vector is
constant BYTES : natural := val'length / 8;
variable ret : std_logic_vector(val'length-1 downto 0);
begin
assert val'length mod 8 = 0
report "length of vector not a multiple of 8"
severity failure;
for i in 0 to BYTES-1 loop
ret((BYTES-i)*8 - 1 downto (BYTES-i-1) * 8) := val((i+1)*8 - 1 downto i*8);
end loop;
return ret;
end function;
end package body;