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base: xiretza:23f0ad777f499099e3ea0a2ec4d37c25d94d345e
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xiretza:main
xiretza:liteeth-wishbone
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compare: xiretza:d2a18e19e54102cab4221859c0a0affe2292796b
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xiretza:liteeth-wishbone
xiretza:main

2 commits
23f0ad777f ... d2a18e19e5

Author SHA1 Message Date
Xiretza
d2a18e19e5 fix: work around ghdl memory inference 2022-06-20 12:01:50 +02:00
Xiretza
c47f81c504 fix: work around ghdl#2078 2022-06-20 12:01:50 +02:00
1 changed files with 13 additions and 6 deletions
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vhdl/splink.vhdl
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@ -168,12 +168,6 @@ begin
receive_state <= DATA;
when DATA =>
if input_bank = BANK_A then
strand_buffer_a(pixels_received)((active_strand+1) * BITS_PER_LED - 1 downto active_strand * BITS_PER_LED) := udp_data(23 downto 0);
else
strand_buffer_b(pixels_received)((active_strand+1) * BITS_PER_LED - 1 downto active_strand * BITS_PER_LED) := udp_data(23 downto 0);
end if;
if pixels_received /= num_pixels - 1 then
pixels_received <= pixels_received + 1;
elsif udp_last then
@ -187,6 +181,19 @@ begin
-- wait until udp_last
end case;
end if;
-- workaround for ghdl#2078
if reset = '0' and udp_valid = '1' and receive_state = DATA then
for i in 0 to NUM_STRANDS-1 loop
if i = active_strand then
if input_bank = BANK_A then
strand_buffer_a(pixels_received)((i+1) * BITS_PER_LED - 1 downto i * BITS_PER_LED) := udp_data(23 downto 0);
else
strand_buffer_b(pixels_received)((i+1) * BITS_PER_LED - 1 downto i * BITS_PER_LED) := udp_data(23 downto 0);
end if;
end if;
end loop;
end if;
end if;
end process;
end architecture;