xiretza/splink
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base: xiretza:0230edd2fb22357d6202bea41f664b9c4634d2dd
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xiretza:main
xiretza:liteeth-wishbone
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compare: xiretza:ea8e6d4b49ccd4667bcdb018421d5fd404079db1
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xiretza:liteeth-wishbone
xiretza:main

No commits in common. "0230edd2fb22357d6202bea41f664b9c4634d2dd" and "ea8e6d4b49ccd4667bcdb018421d5fd404079db1" have entirely different histories.
0230edd2fb ... ea8e6d4b49

3 changed files with 8 additions and 15 deletions
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2
Makefile.nextpnr
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@ -2,7 +2,7 @@ SYNTH_OUTPUT_FILE = $(SYNTH_WORKDIR)/$(YOSYS_MODULE_NAME).json
$(SYNTH_WORKDIR)/%.json: $(VHDL_FILES) $(VERILOG_FILES) | $(SYNTH_WORKDIR) $(GHDL_WORKDIR)/work-obj$(VHDL_STD).cf $(SYNTH_WORKDIR)/%.json: $(VHDL_FILES) $(VERILOG_FILES) | $(SYNTH_WORKDIR) $(GHDL_WORKDIR)/work-obj$(VHDL_STD).cf
$(GHDL) make $(GHDL_FLAGS) $(SYNTH_ENTITY) $(GHDL) make $(GHDL_FLAGS) $(SYNTH_ENTITY)
$(YOSYS) -m $(GHDL_YOSYS_PLUGIN) -l $(SYNTH_WORKDIR)/yosys.log -p 'ghdl $(GHDL_FLAGS) -Werror -Wno-error=binding $(SYNTH_ENTITY); read_verilog $(VERILOG_FILES); chformal -remove; synth_xilinx -nodsp -nosrl -flatten -top $*; write_json $@' $(YOSYS) -m $(GHDL_YOSYS_PLUGIN) -l $(SYNTH_WORKDIR)/yosys.log -p 'ghdl $(GHDL_FLAGS) $(SYNTH_ENTITY); read_verilog $(VERILOG_FILES); chformal -remove; synth_xilinx -nodsp -nosrl -flatten -top $*; write_json $@'
$(SYNTH_WORKDIR)/%.fasm: $(SYNTH_WORKDIR)/%.json $(XDC) $(SYNTH_WORKDIR)/%.fasm: $(SYNTH_WORKDIR)/%.json $(XDC)
$(NEXTPNR) --xdc $(XDC) --json $< --chipdb /usr/share/nextpnr/xilinx-chipdb/$(PART).bin --fasm $@ $(NEXTPNR) --xdc $(XDC) --json $< --chipdb /usr/share/nextpnr/xilinx-chipdb/$(PART).bin --fasm $@

4
vhdl/arty_a7.vhdl
View file

@ -121,7 +121,6 @@ architecture a of arty_a7 is
signal pixel_source_src_ip_address : std_logic_vector(31 downto 0); signal pixel_source_src_ip_address : std_logic_vector(31 downto 0);
signal pixel_source_src_port : std_logic_vector(15 downto 0); signal pixel_source_src_port : std_logic_vector(15 downto 0);
signal pixel_source_length : std_logic_vector(15 downto 0);
signal pixel_source_valid : std_logic; signal pixel_source_valid : std_logic;
signal pixel_source_last : std_logic; signal pixel_source_last : std_logic;
signal pixel_source_data : std_logic_vector(31 downto 0); signal pixel_source_data : std_logic_vector(31 downto 0);
@ -256,7 +255,7 @@ begin
pixel_source_src_ip_address => pixel_source_src_ip_address, pixel_source_src_ip_address => pixel_source_src_ip_address,
pixel_source_src_port => pixel_source_src_port, pixel_source_src_port => pixel_source_src_port,
pixel_source_length => pixel_source_length, pixel_source_length => open,
pixel_source_valid => pixel_source_valid, pixel_source_valid => pixel_source_valid,
pixel_source_last => pixel_source_last, pixel_source_last => pixel_source_last,
pixel_source_last_be => open, pixel_source_last_be => open,
@ -344,7 +343,6 @@ begin
clk => sys_clk, clk => sys_clk,
reset => sys_reset, reset => sys_reset,
udp_length => pixel_source_length,
udp_valid => pixel_source_valid, udp_valid => pixel_source_valid,
udp_last => pixel_source_last, udp_last => pixel_source_last,
udp_data => pixel_source_data_be, udp_data => pixel_source_data_be,

17
vhdl/splink.vhdl
View file

@ -11,7 +11,6 @@ entity splink is
clk : in std_logic; clk : in std_logic;
reset : in std_logic; reset : in std_logic;
udp_length : in std_logic_vector(15 downto 0);
udp_valid : in std_logic; udp_valid : in std_logic;
udp_last : in std_logic; udp_last : in std_logic;
udp_data : in std_logic_vector(31 downto 0); udp_data : in std_logic_vector(31 downto 0);
@ -49,8 +48,6 @@ architecture a of splink is
-- "PIXL" -- "PIXL"
constant MAGIC_NUMBER : std_logic_vector(31 downto 0) := x"5049584c"; constant MAGIC_NUMBER : std_logic_vector(31 downto 0) := x"5049584c";
-- magic + frame num + strand num (4 bytes each)
constant HEADER_LEN : natural := 12;
type receive_state_t is (MAGIC, FRAME_NUM, STRAND_NUM, DATA, DROP); type receive_state_t is (MAGIC, FRAME_NUM, STRAND_NUM, DATA, DROP);
constant RESET_STATE : receive_state_t := MAGIC; constant RESET_STATE : receive_state_t := MAGIC;
@ -143,18 +140,16 @@ begin
case receive_state is case receive_state is
when MAGIC => when MAGIC =>
if udp_data /= MAGIC_NUMBER then if udp_data = MAGIC_NUMBER then
receive_state <= DROP;
else
if (unsigned(udp_length) - HEADER_LEN) / 4 > MAX_STRAND_LEN then
receive_state <= DROP;
else
num_pixels <= (to_integer(unsigned(udp_length)) - HEADER_LEN) / 4;
receive_state <= STRAND_NUM; receive_state <= STRAND_NUM;
end if; else
receive_state <= DROP;
end if; end if;
when STRAND_NUM => when STRAND_NUM =>
-- TODO udp_length, range check with MAX_STRAND_LEN
num_pixels <= MAX_STRAND_LEN;
if unsigned(udp_data) >= NUM_STRANDS then if unsigned(udp_data) >= NUM_STRANDS then
receive_state <= DROP; receive_state <= DROP;
else else