vhdl: use big-endian network byte order

liteeth splits the rx data stream into 4-byte chunks and interprets them as
little-endian 32-bit vecs; similar for the other direction.

vhdl/arty_a7.vhdl

@@ -2,6 +2,8 @@ library ieee;
 use ieee.std_logic_1164.all,
     ieee.numeric_std.all;
 
+use work.util.flip_endianness;
+
 entity arty_a7 is
 	generic (
 		IS_SIMULATION : std_logic := '0'
@@ -242,7 +244,7 @@ begin
 		pixel_sink_last => pixel_sink_last,
 		pixel_sink_last_be => pixel_sink_last_be,
 		pixel_sink_ready => pixel_sink_ready,
-		pixel_sink_data => pixel_sink_data,
+		pixel_sink_data => flip_endianness(pixel_sink_data),
 
 		-- source
 		pixel_source_src_ip_address => pixel_source_src_ip_address,
@@ -337,7 +339,7 @@ begin
 
 			udp_valid => pixel_source_valid,
 			udp_last => pixel_source_last,
-			udp_data => pixel_source_data,
+			udp_data => flip_endianness(pixel_source_data),
 
 			frame_number => frame_number,