diff --git a/vhdl/arty_a7.vhdl b/vhdl/arty_a7.vhdl
index b2c547f..1a8aebd 100644
--- a/vhdl/arty_a7.vhdl
+++ b/vhdl/arty_a7.vhdl
@@ -46,8 +46,8 @@ entity arty_a7 is
 end arty_a7;
 
 architecture a of arty_a7 is
-	constant NUM_DRIVERS: positive := 24;
-	signal drivers: std_logic_vector(NUM_DRIVERS-1 downto 0);
+	constant NUM_STRANDS: positive := 24;
+	signal drivers: std_logic_vector(NUM_STRANDS-1 downto 0);
 
 	component liteeth_core is
 		port (
@@ -317,7 +317,7 @@ begin
 
 	splink: entity work.splink
 		generic map (
-			NUM_DRIVERS => NUM_DRIVERS
+			NUM_STRANDS => NUM_STRANDS
 		)
 		port map (
 			clk => sys_clk,
diff --git a/vhdl/splink.vhdl b/vhdl/splink.vhdl
index cf3c8a2..5462f81 100644
--- a/vhdl/splink.vhdl
+++ b/vhdl/splink.vhdl
@@ -4,14 +4,14 @@ use ieee.numeric_std.all;
 
 entity splink is
 	generic (
-		NUM_DRIVERS : positive;
+		NUM_STRANDS : positive;
 		MAX_STRAND_LEN : positive := 256
 	);
 	port (
 		clk : in std_logic;
 		reset : in std_logic;
 
-		drivers : out std_logic_vector(NUM_DRIVERS-1 downto 0)
+		drivers : out std_logic_vector(NUM_STRANDS-1 downto 0)
 	);
 end entity;