diff --git a/Makefile b/Makefile index 7377677..a520949 100644 --- a/Makefile +++ b/Makefile @@ -52,6 +52,9 @@ SBY = sby -fd '$(SYMBIYOSYS_WORKDIR)' --yosys='$(YOSYS) -m $(GHDL_YOSYS_PLUGIN)' # END OF CONFIGURATION # ==================== +.PHONY: default +default: bitstream + SIM_WAVE = $(SIM_DIR)/$(SIM_ENTITY).ghw # for only capturing select signals SIM_WAVEOPTS = $(SIM_DIR)/$(SIM_ENTITY).waveopt @@ -69,14 +72,8 @@ else $(error Bad PNR toolchain: expected one of symbiflow, nextpnr) endif -# ======= -# PHONIES -# ======= - -.PHONY: all simonly wave - -# default target -all: bitstream +$(GHDL_WORKDIR) $(SYNTH_WORKDIR): + mkdir -p $@ $(GHDL_WORKDIR)/work-obj$(VHDL_STD).cf: | $(GHDL_WORKDIR) $(GHDL) import $(GHDL_FLAGS) $(VHDL_FILES) @@ -84,42 +81,42 @@ $(GHDL_WORKDIR)/work-obj$(VHDL_STD).cf: | $(GHDL_WORKDIR) $(LITEX_WORKDIR)/gateware/liteeth_core.v: gen_liteeth.py ./gen_liteeth.py --output-dir $(LITEX_WORKDIR) +# ======= +# PHONIES +# ======= + +.PHONY: simonly simonly: $(VHDL_FILES) | $(GHDL_WORKDIR)/work-obj$(VHDL_STD).cf $(GHDL) make $(GHDL_FLAGS) $(SIM_ENTITY) $(GHDL) run $(GHDL_FLAGS) $(SIM_ENTITY) $(SIM_RUN_FLAGS) +.PHONY: wave wave: $(VHDL_FILES) $(GHDL) make $(GHDL_FLAGS) $(SIM_ENTITY) $(GHDL) run $(GHDL_FLAGS) $(SIM_ENTITY) $(SIM_RUN_FLAGS) --wave=$(SIM_WAVE) $(GTKWAVE) $(SIM_WAVE) $(SIM_WAVE_SAVE) -.PHONY: check check-formal +.PHONY: check check: check-formal +.PHONY: check-formal check-formal: $(foreach f,$(SBY_FILES),$(SBY) $(f)) -.PHONY: synth show bitstream flash +.PHONY: synth synth: $(SYNTH_OUTPUT_FILE) +.PHONY: show show: $(SYNTH_OUTPUT_FILE) $(YOSYS) -p show $< +.PHONY: bitstream bitstream: $(SYNTH_WORKDIR)/$(YOSYS_MODULE_NAME).bit +.PHONY: flash flash: $(SYNTH_WORKDIR)/$(YOSYS_MODULE_NAME).bit $(OPENFPGALOADER) -b arty $< .PHONY: clean clean: rm -rf $(WORKDIR) - -$(GHDL_WORKDIR) $(SYNTH_WORKDIR): - mkdir -p $@ - -.PHONY: echo-ghdl-flags echo-sim-run-flags -echo-ghdl-flags: - @echo $(GHDL_FLAGS) - -echo-sim-run-flags: - @echo $(SIM_RUN_FLAGS)