diff --git a/Makefile.symbiflow b/Makefile.symbiflow
index a8d23d3..e866cf2 100644
--- a/Makefile.symbiflow
+++ b/Makefile.symbiflow
@@ -2,7 +2,7 @@ SYNTH_OUTPUT_FILE = $(SYNTH_WORKDIR)/$(YOSYS_MODULE_NAME).eblif
 
 $(SYNTH_WORKDIR)/%.il: $(VHDL_FILES) $(VERILOG_FILES) | $(SYNTH_WORKDIR) $(GHDL_WORKDIR)/work-obj$(VHDL_STD).cf
 	$(GHDL) make $(GHDL_FLAGS) $(SYNTH_ENTITY)
-	$(YOSYS) -m $(GHDL_YOSYS_PLUGIN) -p 'read_verilog -defer $(VERILOG_FILES); ghdl $(GHDL_FLAGS) $(SYNTH_ENTITY); chformal -remove; check -assert; write_rtlil $@'
+	$(YOSYS) -m $(GHDL_YOSYS_PLUGIN) -p 'read_verilog $(VERILOG_FILES); ghdl $(GHDL_FLAGS) $(SYNTH_ENTITY); chformal -remove; check -assert; write_rtlil $@'
 
 $(SYNTH_WORKDIR)/%.eblif: $(SYNTH_WORKDIR)/%.il $(XDC)
 	cd $(SYNTH_WORKDIR) && symbiflow_synth -d artix7 -t $* -v $< -p $(PART) -x $(XDC)