2022-06-03 19:11:07 +02:00
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library ieee;
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use ieee.std_logic_1164.all,
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ieee.numeric_std.all;
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entity arty_a7 is
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generic (
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IS_SIMULATION : std_logic := '0'
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);
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port (
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n_reset : in std_logic;
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buttons : in std_logic_vector(3 downto 0);
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switches : in std_logic_vector(3 downto 0);
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leds_simple : out std_logic_vector(3 downto 0);
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led0, led1, led2, led3 : out std_logic_vector(2 downto 0);
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-- Pmod connectors - A+D standard, B+C high-speed.
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-- Defined as inputs by default for safety, change
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-- when necessary
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pmod_a : in std_logic_vector(7 downto 0);
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pmod_b : in std_logic_vector(7 downto 0);
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pmod_c : in std_logic_vector(7 downto 0);
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pmod_d : in std_logic_vector(7 downto 0);
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clock_100mhz : in std_logic;
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uart_rx : in std_logic;
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uart_tx : out std_logic;
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mii_clk_25mhz : out std_logic;
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mii_n_reset : out std_logic;
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mii_mdio : inout std_logic;
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mii_mdc : out std_logic;
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mii_rx_clk : in std_logic;
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mii_rx_er : in std_logic;
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mii_rx_dv : in std_logic;
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mii_rx_data : in std_logic_vector(3 downto 0);
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mii_tx_clk : in std_logic;
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mii_tx_en : out std_logic;
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mii_tx_data : out std_logic_vector(3 downto 0);
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mii_col : in std_logic;
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mii_crs : in std_logic;
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ck_dig_l : inout std_logic_vector(13 downto 0);
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ck_dig_h : inout std_logic_vector(41 downto 26)
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);
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end arty_a7;
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architecture a of arty_a7 is
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constant NUM_DRIVERS: positive := 16;
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signal drivers: std_logic_vector(NUM_DRIVERS-1 downto 0);
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2022-06-04 21:46:16 +02:00
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component liteeth_core is
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port (
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sys_clock : in std_logic;
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sys_reset : in std_logic;
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mii_eth_clocks_tx : in std_logic;
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mii_eth_clocks_rx : in std_logic;
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mii_eth_rst_n : out std_logic;
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mii_eth_mdio : inout std_logic;
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mii_eth_mdc : out std_logic;
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mii_eth_rx_dv : in std_logic;
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mii_eth_rx_er : in std_logic;
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mii_eth_rx_data : in std_logic_vector(3 downto 0);
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mii_eth_tx_en : out std_logic;
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mii_eth_tx_data : out std_logic_vector(3 downto 0);
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mii_eth_col : in std_logic;
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mii_eth_crs : in std_logic;
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ip_address : in std_logic_vector(31 downto 0);
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dhcp_ip_address : in std_logic_vector(31 downto 0);
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dhcp_sink_valid : in std_logic;
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dhcp_sink_last : in std_logic;
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dhcp_sink_ready : out std_logic;
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dhcp_sink_data : in std_logic_vector(31 downto 0);
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dhcp_source_valid : out std_logic;
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dhcp_source_last : out std_logic;
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dhcp_source_ready : in std_logic;
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dhcp_source_data : out std_logic_vector(31 downto 0)
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);
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end component;
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signal dhcp_source_valid : std_logic;
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component PLLE2_BASE
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generic (
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CLKFBOUT_MULT : integer;
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DIVCLK_DIVIDE : integer;
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CLKIN1_PERIOD : real;
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CLKOUT0_DIVIDE : integer := 0;
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CLKOUT0_DUTY_CYCLE : real := 0.5;
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CLKOUT0_PHASE : real := 0.0;
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CLKOUT1_DIVIDE : integer := 0;
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CLKOUT1_DUTY_CYCLE : real := 0.5;
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CLKOUT1_PHASE : real := 0.0;
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CLKOUT2_DIVIDE : integer := 0;
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CLKOUT2_DUTY_CYCLE : real := 0.5;
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CLKOUT2_PHASE : real := 0.0;
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CLKOUT3_DIVIDE : integer := 0;
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CLKOUT3_DUTY_CYCLE : real := 0.5;
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CLKOUT3_PHASE : real := 0.0;
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CLKOUT4_DIVIDE : integer := 0;
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CLKOUT4_DUTY_CYCLE : real := 0.5;
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CLKOUT4_PHASE : real := 0.0;
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CLKOUT5_DIVIDE : integer := 0;
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CLKOUT5_DUTY_CYCLE : real := 0.5;
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CLKOUT5_PHASE : real := 0.0
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);
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port (
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RST : in std_logic;
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PWRDWN : in std_logic;
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LOCKED : out std_logic;
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CLKIN1 : in std_logic;
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CLKFBIN : in std_logic;
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CLKFBOUT : out std_logic;
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CLKOUT0 : out std_logic;
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CLKOUT1 : out std_logic;
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CLKOUT2 : out std_logic;
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CLKOUT3 : out std_logic;
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CLKOUT4 : out std_logic;
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CLKOUT5 : out std_logic
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);
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end component PLLE2_BASE;
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signal pll_feedback : std_logic;
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signal unbuf_clk_sys : std_logic;
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signal clk_sys : std_logic;
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component BUFG
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port (
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I : in std_logic;
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O : out std_logic
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);
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end component BUFG;
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2022-06-03 19:11:07 +02:00
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begin
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--leds_simple <= (others => '0');
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2022-06-04 21:46:16 +02:00
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--led0 <= (others => '0');
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2022-06-03 19:11:07 +02:00
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led1 <= (others => '0');
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led2 <= (others => '0');
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led3 <= (others => '0');
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uart_tx <= '0';
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ck_dig_l <= (others => 'Z');
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ck_dig_h <= (others => 'Z');
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leds_simple <= drivers(3 downto 0);
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2022-06-04 21:46:16 +02:00
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liteeth_inst: liteeth_core port map (
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sys_clock => clk_sys,
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sys_reset => '0',
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mii_eth_clocks_tx => mii_tx_clk,
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mii_eth_clocks_rx => mii_rx_clk,
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mii_eth_rst_n => mii_n_reset,
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mii_eth_mdio => mii_mdio,
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mii_eth_mdc => mii_mdc,
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mii_eth_rx_dv => mii_rx_dv,
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mii_eth_rx_er => mii_rx_er,
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mii_eth_rx_data => mii_rx_data,
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mii_eth_tx_en => mii_tx_en,
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mii_eth_tx_data => mii_tx_data,
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mii_eth_col => mii_col,
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mii_eth_crs => mii_crs,
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ip_address => x"0a141e28", -- 10.20.30.40
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dhcp_ip_address => x"0a141e29", -- 10.20.30.41
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dhcp_sink_valid => '0',
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dhcp_sink_last => '1',
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dhcp_sink_data => x"cafebebe",
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dhcp_source_valid => dhcp_source_valid,
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dhcp_source_ready => '1'
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);
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-- 800 MHz VCO
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-- 80 MHz system clock
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-- 25 MHz MII clock
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pll_inst: PLLE2_BASE
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generic map (
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CLKFBOUT_MULT => 8,
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DIVCLK_DIVIDE => 1,
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CLKIN1_PERIOD => 10.0,
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CLKOUT0_DIVIDE => 10,
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CLKOUT1_DIVIDE => 32,
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CLKOUT2_DIVIDE => 10,
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CLKOUT3_DIVIDE => 10,
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CLKOUT4_DIVIDE => 10,
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CLKOUT5_DIVIDE => 10
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)
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port map (
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RST => '0',
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PWRDWN => '0',
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CLKIN1 => clock_100mhz,
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CLKFBIN => pll_feedback,
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CLKFBOUT => pll_feedback,
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CLKOUT0 => unbuf_clk_sys,
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CLKOUT1 => mii_clk_25mhz
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);
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bufg_clk_sys: BUFG
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port map (
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I => unbuf_clk_sys,
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O => clk_sys
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);
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2022-06-03 19:11:07 +02:00
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splink: entity work.splink
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generic map (
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NUM_DRIVERS => NUM_DRIVERS
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)
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port map (
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2022-06-04 21:46:16 +02:00
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clk => clk_sys,
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2022-06-03 19:11:07 +02:00
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reset => not n_reset,
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drivers => drivers
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);
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end architecture;
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