2022-06-03 19:11:07 +02:00
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SYNTH_OUTPUT_FILE = $(SYNTH_WORKDIR)/$(YOSYS_MODULE_NAME).eblif
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$(SYNTH_WORKDIR)/%.il: $(VHDL_FILES) $(VERILOG_FILES) | $(SYNTH_WORKDIR) $(GHDL_WORKDIR)/work-obj$(VHDL_STD).cf
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$(GHDL) make $(GHDL_FLAGS) $(SYNTH_ENTITY)
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2022-06-03 22:18:09 +02:00
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$(YOSYS) -m $(GHDL_YOSYS_PLUGIN) -p 'read_verilog $(VERILOG_FILES); ghdl $(GHDL_FLAGS) $(SYNTH_ENTITY); chformal -remove; check -assert; write_rtlil $@'
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2022-06-03 19:11:07 +02:00
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$(SYNTH_WORKDIR)/%.eblif: $(SYNTH_WORKDIR)/%.il $(XDC)
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cd $(SYNTH_WORKDIR) && symbiflow_synth -d artix7 -t $* -v $< -p $(PART) -x $(XDC)
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$(SYNTH_WORKDIR)/%.net: $(SYNTH_WORKDIR)/%.eblif
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cd $(SYNTH_WORKDIR) && symbiflow_pack -d xc7a50t_test -e $<
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$(SYNTH_WORKDIR)/%.place: $(SYNTH_WORKDIR)/%.eblif $(SYNTH_WORKDIR)/%.net
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cd $(SYNTH_WORKDIR) && symbiflow_place -d xc7a50t_test -e $< -n $(word 2,$^) -P $(PART)
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$(SYNTH_WORKDIR)/%.route: $(SYNTH_WORKDIR)/%.eblif $(SYNTH_WORKDIR)/%.place
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cd $(SYNTH_WORKDIR) && symbiflow_route -d xc7a50t_test -e $<
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$(SYNTH_WORKDIR)/%.fasm: $(SYNTH_WORKDIR)/%.eblif $(SYNTH_WORKDIR)/%.route
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cd $(SYNTH_WORKDIR) && symbiflow_write_fasm -d xc7a50t_test -e $<
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$(SYNTH_WORKDIR)/%.bit: $(SYNTH_WORKDIR)/%.fasm
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cd $(SYNTH_WORKDIR) && symbiflow_write_bitstream -d artix7 -f $< -p $(PART) -b $@
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