87 lines
1.5 KiB
VHDL
87 lines
1.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all,
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ieee.numeric_std.all;
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use std.textio.all;
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entity sim is
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generic (
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COUNTER_WIDTH : positive := 12;
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STEP : natural range 1 to 2
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);
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end entity;
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architecture a of sim is
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signal char_in : character;
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signal clk, reset, is_record : std_logic;
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signal num_verified : unsigned(COUNTER_WIDTH-1 downto 0);
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procedure print(s: string) is
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variable l : line;
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begin
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write(l, s);
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writeline(output, l);
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end procedure;
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begin
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process
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variable current_line : line;
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variable current_char : character;
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variable good : boolean;
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procedure cycle_clock is
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begin
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wait for 10 ns;
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clk <= '0';
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wait for 10 ns;
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clk <= '1';
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wait for 0 ns;
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end procedure;
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begin
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clk <= '0';
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is_record <= '0';
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char_in <= NUL;
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reset <= '1';
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cycle_clock;
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reset <= '0';
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cycle_clock;
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lines_loop: loop
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exit lines_loop when endfile(input);
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readline(input, current_line);
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is_record <= '1';
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chars_loop: loop
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read(current_line, current_char, good);
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exit chars_loop when not good;
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char_in <= current_char;
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cycle_clock;
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end loop;
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is_record <= '0';
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cycle_clock;
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end loop;
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cycle_clock;
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print(to_string(to_integer(num_verified)));
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wait;
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end process;
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top: entity work.top
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generic map (
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COUNTER_WIDTH => COUNTER_WIDTH,
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STEP => STEP
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)
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port map (
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clk => clk,
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reset => reset,
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char => char_in,
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is_record => is_record,
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num_verified => num_verified
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);
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end architecture;
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