59 lines
1 KiB
VHDL
59 lines
1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity verifier is
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port (
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clk : in std_logic;
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reset : in std_logic;
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is_data : in std_logic;
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num1, num2 : in natural range 0 to 99;
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letter : in character;
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char : in character;
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verified : out std_logic
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);
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end entity;
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architecture step1 of verifier is
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signal count : natural range 0 to 99;
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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if reset then
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count <= 0;
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elsif is_data then
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if char = letter then
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count <= count + 1;
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end if;
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end if;
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end if;
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end process;
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verified <= '1' when num1 <= count and count <= num2 else '0';
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end architecture;
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architecture step2 of verifier is
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signal count : natural range 1 to 99;
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signal parity : std_logic;
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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if reset then
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count <= 1;
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parity <= '0';
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elsif is_data then
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count <= count + 1;
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if (count = num1 or count = num2) and char = letter then
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parity <= not parity;
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end if;
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end if;
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end if;
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end process;
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verified <= parity;
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end architecture;
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