85 lines
1.8 KiB
VHDL
85 lines
1.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all,
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ieee.numeric_std.all;
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entity top is
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generic (
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COUNTER_WIDTH : positive;
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STEP : natural range 1 to 2
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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char : in character;
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is_record : in std_logic;
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num_verified : out unsigned(COUNTER_WIDTH-1 downto 0)
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);
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end entity;
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architecture behaviour of top is
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signal is_data : std_logic;
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signal num1, num2 : natural range 0 to 99;
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signal letter : character;
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signal prev_is_record : std_logic;
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signal record_ended : std_logic;
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signal verified : std_logic;
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begin
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record_ended <= prev_is_record and not is_record;
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parser_inst: entity work.parser
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port map (
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clk => clk,
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reset => reset,
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is_record => is_record,
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is_data => is_data,
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char => char,
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num1 => num1,
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num2 => num2,
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letter => letter
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);
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generate_verifier: if step = 1 generate
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verifier_inst: entity work.verifier(step1)
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port map (
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clk => clk,
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reset => reset or record_ended,
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is_data => is_data,
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num1 => num1,
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num2 => num2,
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letter => letter,
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char => char,
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verified => verified
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);
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elsif step = 2 generate
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verifier_inst: entity work.verifier(step2)
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port map (
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clk => clk,
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reset => reset or record_ended,
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is_data => is_data,
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num1 => num1,
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num2 => num2,
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letter => letter,
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char => char,
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verified => verified
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);
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else generate
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assert false report "Bad value for ""step""" severity failure;
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end generate;
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process(clk)
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begin
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if rising_edge(clk) then
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prev_is_record <= is_record;
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if reset then
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prev_is_record <= '0';
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num_verified <= (others => '0');
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elsif record_ended and verified then
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num_verified <= num_verified + 1;
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end if;
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end if;
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end process;
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end architecture;
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