diff --git a/day1/day1.py b/day1/day1.py
index b7a8f39..a2fd1ef 100755
--- a/day1/day1.py
+++ b/day1/day1.py
@@ -16,7 +16,6 @@ def find_summing(arity: int, nums: Iterable[int]) -> int:
     return product(next(filter(lambda xs: sum(xs) == 2020, itertools.permutations(nums, r=arity))))
 
 if __name__ == '__main__':
-    with open(sys.argv[1], 'r') as f:
-        nums = [int(n) for n in f.readlines()]
+    nums = [int(n) for n in sys.stdin.readlines()]
     print(find_summing(2, nums))
     print(find_summing(3, nums))
diff --git a/day2/day2.py b/day2/day2.py
index feef90c..c739680 100755
--- a/day2/day2.py
+++ b/day2/day2.py
@@ -1,5 +1,6 @@
 #!/usr/bin/env python
 import re
+import sys
 from collections import Counter
 
 r = re.compile(r'(\d+)-(\d+) (.): (.*)')
@@ -15,8 +16,7 @@ def do_line(req_func, line):
     return req_func(int(min_required), int(max_required), letter, password)
 
 if __name__ == '__main__':
-    with open('input.txt', 'r') as f:
-        lines = list(f.readlines())
+    lines = list(sys.stdin.readlines())
 
     for func in (requirements_met_1, requirements_met_2):
         print(len(list(filter(lambda line: do_line(func, line), lines))))
diff --git a/day2/vhdl/run.sh b/day2/vhdl/run.sh
index 7ab777d..530ec7d 100755
--- a/day2/vhdl/run.sh
+++ b/day2/vhdl/run.sh
@@ -2,14 +2,15 @@
 
 set -eu
 
+INPUT=$1
 GHDLFLAGS="--std=08 --workdir=workdir"
 
 mkdir -p workdir
 
 ghdl remove $GHDLFLAGS
 ghdl analyze $GHDLFLAGS parser.vhd verifier.vhd top.vhd sim.vhd
-ghdl elab-run $GHDLFLAGS sim -gSTEP=1 -gFILENAME="../input.txt"
-ghdl elab-run $GHDLFLAGS sim -gSTEP=2 -gFILENAME="../input.txt"
+ghdl elab-run $GHDLFLAGS sim -gSTEP=1 < "$INPUT"
+ghdl elab-run $GHDLFLAGS sim -gSTEP=2 < "$INPUT"
 
 echo "Synthesized: "
 
@@ -17,5 +18,5 @@ for step in 1 2; do
 	ghdl remove $GHDLFLAGS
 	ghdl synth $GHDLFLAGS -gCOUNTER_WIDTH=12 -gSTEP="$step" parser.vhd verifier.vhd top.vhd -e top > top_syn.vhd
 	ghdl analyze $GHDLFLAGS top_syn.vhd sim.vhd
-	ghdl elab-run $GHDLFLAGS sim -gSTEP="$step" -gFILENAME="../input.txt" --ieee-asserts=disable-at-0
+	ghdl elab-run $GHDLFLAGS sim -gSTEP="$step" --ieee-asserts=disable < "$INPUT"
 done
diff --git a/day2/vhdl/sim.vhd b/day2/vhdl/sim.vhd
index 3b4299b..baf7e5e 100644
--- a/day2/vhdl/sim.vhd
+++ b/day2/vhdl/sim.vhd
@@ -6,14 +6,12 @@ use std.textio.all;
 
 entity sim is
 	generic (
-		FILENAME : string := "input.txt";
 		COUNTER_WIDTH : positive := 12;
 		STEP : natural range 1 to 2
 	);
 end entity;
 
 architecture a of sim is
-	file file_handle : text open read_mode is FILENAME;
 	signal char_in : character;
 	signal clk, reset, is_record : std_logic;
 	signal num_verified : unsigned(COUNTER_WIDTH-1 downto 0);
@@ -49,8 +47,8 @@ begin
 		cycle_clock;
 
 		lines_loop: loop
-			exit lines_loop when endfile(file_handle);
-			readline(file_handle, current_line);
+			exit lines_loop when endfile(input);
+			readline(input, current_line);
 
 			is_record <= '1';
 
diff --git a/day3/day3.py b/day3/day3.py
index 1aaa4b9..ab2c3ae 100755
--- a/day3/day3.py
+++ b/day3/day3.py
@@ -1,5 +1,7 @@
 #!/usr/bin/env python
 
+import sys
+
 def count_trees(right, down, lines):
     n = 0
     for i, line in enumerate(lines[::down]):
@@ -9,8 +11,7 @@ def count_trees(right, down, lines):
     return n
 
 if __name__ == '__main__':
-    with open('input.txt', 'r') as f:
-        lines = [line.strip() for line in f.readlines()]
+    lines = [line.strip() for line in sys.stdin.readlines()]
 
     print(count_trees(3, 1, lines))
 
diff --git a/day4/day4.py b/day4/day4.py
index 208064f..3fd8e20 100755
--- a/day4/day4.py
+++ b/day4/day4.py
@@ -1,5 +1,7 @@
 #!/usr/bin/env python
 
+import sys
+
 def within(a, b, x):
     return a <= x <= b
 
@@ -48,8 +50,7 @@ def split_on(f, it):
         yield current_part
 
 if __name__ == '__main__':
-    with open('input.txt', 'r') as f:
-        lines = [line.strip() for line in f.readlines()]
+    lines = [line.strip() for line in sys.stdin.readlines()]
 
     specs = list(' '.join(lines) for lines in split_on(lambda l: l == "", lines))