aoc2020/day2/vhdl/sim.vhd

library ieee;
use ieee.std_logic_1164.all,
    ieee.numeric_std.all;

use std.textio.all;

entity sim is
	generic (
		COUNTER_WIDTH : positive := 12;
		STEP : natural range 1 to 2
	);
end entity;

architecture a of sim is
	signal char_in : character;
	signal clk, reset, is_record : std_logic;
	signal num_verified : unsigned(COUNTER_WIDTH-1 downto 0);

	procedure print(s: string) is
		variable l : line;
	begin
		write(l, s);
		writeline(output, l);
	end procedure;
begin
	process
		variable current_line : line;
		variable current_char : character;
		variable good : boolean;

		procedure cycle_clock is
		begin
			wait for 10 ns;
			clk <= '0';
			wait for 10 ns;
			clk <= '1';
			wait for 0 ns;
		end procedure;
	begin
		clk <= '0';
		is_record <= '0';
		char_in <= NUL;

		reset <= '1';
		cycle_clock;
		reset <= '0';
		cycle_clock;

		lines_loop: loop
			exit lines_loop when endfile(input);
			readline(input, current_line);

			is_record <= '1';

			chars_loop: loop
				read(current_line, current_char, good);
				exit chars_loop when not good;

				char_in <= current_char;
				cycle_clock;
			end loop;

			is_record <= '0';
			cycle_clock;
		end loop;

		cycle_clock;

		print(to_string(to_integer(num_verified)));

		wait;
	end process;

	top: entity work.top
		generic map (
			COUNTER_WIDTH => COUNTER_WIDTH,
			STEP => STEP
		)
		port map (
			clk => clk,
			reset => reset,
			char => char_in,
			is_record => is_record,
			num_verified => num_verified
		);
end architecture;