17 lines
293 B
VHDL
17 lines
293 B
VHDL
configuration day2 of sim is
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for aoc_stdio
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for dut_inst: dut
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use entity work.top port map (
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clk => clk,
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reset => reset,
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char => char,
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input_valid => input_valid,
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num_verified => output,
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output_valid => output_valid
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);
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end for;
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end for;
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end configuration;
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