Xiretza d60b8c5371 common: add VHDL testbench and runner		2021-12-01 14:02:09 +01:00
..
vhdl	common: add VHDL testbench and runner	2021-12-01 14:02:09 +01:00
day2.hs	2020 day2/haskell: add solution	2021-12-01 09:08:24 +01:00
day2.py	read problem inputs from stdin	2021-12-01 08:54:50 +01:00