100 lines
1.8 KiB
VHDL
100 lines
1.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all,
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ieee.numeric_std.all;
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use std.textio.all;
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entity sim is
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generic (
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OUTPUT_WIDTH : positive;
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STEP : natural range 1 to 2
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);
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end entity;
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architecture aoc_stdio of sim is
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type char_file_t is file of character;
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file stdin : char_file_t open READ_MODE is "STD_INPUT";
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signal char_in : character;
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signal clk, reset, input_valid, output_valid : std_logic;
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signal output : unsigned(OUTPUT_WIDTH-1 downto 0);
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procedure print(s: string) is
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variable l : line;
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begin
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write(l, s);
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writeline(std.textio.output, l);
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end procedure;
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component dut is
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generic (
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OUTPUT_WIDTH : positive;
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STEP : natural range 1 to 2
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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char : in character;
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input_valid : in std_logic;
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output : out unsigned(OUTPUT_WIDTH-1 downto 0);
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output_valid : out std_logic
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);
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end component;
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begin
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process
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variable current_char : character;
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variable good : boolean;
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procedure cycle_clock is
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begin
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wait for 10 ns;
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clk <= '0';
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wait for 10 ns;
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clk <= '1';
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wait for 0 ns;
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end procedure;
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begin
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clk <= '0';
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input_valid <= '0';
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char_in <= NUL;
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reset <= '1';
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cycle_clock;
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reset <= '0';
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cycle_clock;
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input_valid <= '1';
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chars_loop: while not endfile(stdin) loop
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read(stdin, current_char);
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char_in <= current_char;
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cycle_clock;
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end loop;
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input_valid <= '0';
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cycle_clock;
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cycle_clock;
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assert output_valid report "Output was not valid at end of simulation" severity failure;
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print(to_string(to_integer(output)));
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wait;
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end process;
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dut_inst: dut
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generic map (
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OUTPUT_WIDTH => OUTPUT_WIDTH,
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STEP => STEP
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)
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port map (
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clk => clk,
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reset => reset,
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char => char_in,
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input_valid => input_valid,
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output => output,
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output_valid => output_valid
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);
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end architecture;
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