12 lines
226 B
VHDL
12 lines
226 B
VHDL
configuration day1 of sim is
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for aoc_stdio
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for dut_inst : dut
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use entity work.top generic map (
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MAX_INPUT_DIGITS => 6,
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OUTPUT_WIDTH => OUTPUT_WIDTH,
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STEP => STEP
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);
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end for;
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end for;
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end configuration;
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