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8 changed files with 15 additions and 169 deletions
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18
2020/day2/vhdl/parser.vhdl
View file

@ -1,8 +1,6 @@
library ieee;
use ieee.std_logic_1164.all;
use work.util.all;
entity parser is
port (
clk : in std_logic;
@ -23,13 +21,23 @@ architecture behaviour of parser is
type state_t is (S_NUM1, S_NUM2, S_LETTER, S_COLON, S_END_SPACE, S_DATA);
signal state : state_t := S_NUM1;
type multiples_lookup_t is array(digit_t) of natural range 0 to 90;
subtype digit is natural range 0 to 9;
type multiples_lookup_t is array(digit) of natural range 0 to 90;
constant TEN_MULTIPLES : multiples_lookup_t := (0, 10, 20, 30, 40, 50, 60, 70, 80, 90);
-- most significant digit of number
signal prev_digit : digit_t := 0;
signal current_digit : digit_t;
signal prev_digit : digit := 0;
signal current_digit : digit;
signal complete_num : natural range 0 to 99;
function char_to_digit(input : in character) return digit is
begin
if input >= '0' and input <= '9' then
return character'pos(input) - character'pos('0');
else
return 0;
end if;
end function;
begin
current_digit <= char_to_digit(char);
complete_num <= TEN_MULTIPLES(prev_digit) + current_digit;

2
2021/day1/vhdl/.gitignore vendored
View file

@ -1,2 +0,0 @@
day1
workdir/

11
2021/day1/vhdl/day1.vhdl
View file

@ -1,11 +0,0 @@
configuration day1 of sim is
for aoc_stdio
for dut_inst : dut
use entity work.top generic map (
MAX_INPUT_DIGITS => 6,
OUTPUT_WIDTH => OUTPUT_WIDTH,
STEP => STEP
);
end for;
end for;
end configuration;

8
2021/day1/vhdl/run.sh
View file

@ -1,8 +0,0 @@
#!/bin/bash
source "$COMMON_DIR/vhdl_run.sh"
cd "$(dirname "${BASH_SOURCE[0]}")"
DUT_OUTPUT_WIDTH=12
test_sim day1 top.vhdl

55
2021/day1/vhdl/sim.gtkw
View file

@ -1,55 +0,0 @@
[*]
[*] GTKWave Analyzer v3.3.109 (w)1999-2020 BSI
[*] Wed Dec 1 13:50:21 2021
[*]
[dumpfile] "/home/xiretza/dev/advent-of-code/2021/day1/vhdl/workdir/sim1.ghw"
[dumpfile_mtime] "Wed Dec 1 13:48:36 2021"
[dumpfile_size] 235598
[savefile] "/home/xiretza/dev/advent-of-code/2021/day1/vhdl/sim.gtkw"
[timestart] 11375200000
[size] 1920 1035
[pos] -1 -1
*-26.627251 11673700000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.sim.
[treeopen] top.sim.dut_inst.
[treeopen] top.sim.dut_inst.window.
[sst_width] 221
[signals_width] 173
[sst_expanded] 1
[sst_vpaned_height] 296
@28
top.sim.clk
top.sim.reset
@420
top.sim.char_in
@200
-
@420
top.sim.dut_inst.window[0][0]
top.sim.dut_inst.window[0][1]
top.sim.dut_inst.window[0][2]
top.sim.dut_inst.window[0][3]
top.sim.dut_inst.window[0][4]
top.sim.dut_inst.window[0][5]
@200
-
@420
top.sim.dut_inst.window[1][0]
top.sim.dut_inst.window[1][1]
top.sim.dut_inst.window[1][2]
@421
top.sim.dut_inst.window[1][3]
@420
top.sim.dut_inst.window[1][4]
top.sim.dut_inst.window[1][5]
@200
-
@28
top.sim.input_valid
@22
#{top.sim.output[11:0]} top.sim.output[11] top.sim.output[10] top.sim.output[9] top.sim.output[8] top.sim.output[7] top.sim.output[6] top.sim.output[5] top.sim.output[4] top.sim.output[3] top.sim.output[2] top.sim.output[1] top.sim.output[0]
@28
top.sim.output_valid
[pattern_trace] 1
[pattern_trace] 0

71
2021/day1/vhdl/top.vhdl
View file

@ -1,71 +0,0 @@
library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
use work.util.all;
entity top is
generic (
MAX_INPUT_DIGITS : positive;
OUTPUT_WIDTH : positive;
STEP : natural range 1 to 2
);
port (
clk : in std_logic;
reset : in std_logic;
char : in character;
input_valid : in std_logic;
output : out unsigned(OUTPUT_WIDTH-1 downto 0);
output_valid : out std_logic
);
end entity;
architecture arch of top is
function get_window_size return positive is
begin
if STEP = 1 then
return 1;
else
return 3;
end if;
end function;
constant WINDOW_SIZE : positive := get_window_size;
type number_t is array(MAX_INPUT_DIGITS-1 downto 0) of digit_t;
type window_t is array(0 to WINDOW_SIZE) of number_t;
signal window : window_t;
signal window_countdown : natural range WINDOW_SIZE downto 0 := 0;
begin
process(clk)
begin
if rising_edge(clk) then
if reset then
output <= (others => '0');
output_valid <= '1';
window_countdown <= 0;
elsif input_valid then
output_valid <= '0';
if char = LF then
if window_countdown = WINDOW_SIZE then
if window(0) > window(window'high) then
output <= output + 1;
end if;
output_valid <= '1';
else
window_countdown <= window_countdown + 1;
end if;
window <= number_t'(others => 0) & window(0 to window'high-1);
else
window(0) <= window(0)(MAX_INPUT_DIGITS-2 downto 0) & char_to_digit(char);
end if;
end if;
end if;
end process;
end architecture;

15
common/util.vhdl
View file

@ -1,15 +0,0 @@
package util is
subtype digit_t is natural range 0 to 9;
function char_to_digit(input : in character) return digit_t;
end package;
package body util is
function char_to_digit(input : in character) return digit_t is
begin
if input >= '0' and input <= '9' then
return character'pos(input) - character'pos('0');
else
return 0;
end if;
end function;
end package body;

4
common/vhdl_run.sh
View file

@ -13,7 +13,7 @@ test_synth() {
for step in 1 2; do
ghdl remove $GHDLFLAGS
ghdl synth $GHDLFLAGS -gOUTPUT_WIDTH="$DUT_OUTPUT_WIDTH" -gSTEP="$step" "$COMMON_DIR/util.vhdl" "$@" -e top > "$workdir/top_syn.vhdl" 2>/dev/null
ghdl synth $GHDLFLAGS -gOUTPUT_WIDTH="$DUT_OUTPUT_WIDTH" -gSTEP="$step" "$@" -e top > "$workdir/top_syn.vhdl" 2>/dev/null
ghdl analyze $GHDLFLAGS "$workdir/top_syn.vhdl" "$COMMON_DIR/testbench.vhdl" "$config_name.vhdl"
ghdl elab-run $GHDLFLAGS "$config_name" -gOUTPUT_WIDTH="$DUT_OUTPUT_WIDTH" --wave="$workdir/synth$step.ghw" --ieee-asserts=disable < "$INPUT"
done
@ -23,7 +23,7 @@ test_sim() {
local config_name=$1; shift
ghdl remove $GHDLFLAGS
ghdl analyze $GHDLFLAGS "$COMMON_DIR/testbench.vhdl" "$COMMON_DIR/util.vhdl" "$@" "$config_name.vhdl"
ghdl analyze $GHDLFLAGS "$COMMON_DIR/testbench.vhdl" "$@" "$config_name.vhdl"
for step in 1 2; do
ghdl elab-run $GHDLFLAGS "$config_name" -gOUTPUT_WIDTH="$DUT_OUTPUT_WIDTH" -gSTEP="$step" --wave="$workdir/sim$step.ghw" < "$INPUT"
done