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day2/vhdl: don't simulate synthesized design by default

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Xiretza 2020-12-06 12:12:15 +01:00
parent 6bcb64280d
commit f989d052be
1 changed files with 13 additions and 12 deletions
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21
2020/day2/vhdl/run.sh
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@ -3,20 +3,21 @@
set -eu
INPUT=$1
MODE=${2:-}
GHDLFLAGS="--std=08 --workdir=workdir"
mkdir -p workdir
ghdl remove $GHDLFLAGS
ghdl analyze $GHDLFLAGS parser.vhd verifier.vhd top.vhd sim.vhd
ghdl elab-run $GHDLFLAGS sim -gSTEP=1 < "$INPUT"
ghdl elab-run $GHDLFLAGS sim -gSTEP=2 < "$INPUT"
echo "Synthesized: "
for step in 1 2; do
if [[ $MODE = "--synth" ]]; then
for step in 1 2; do
ghdl remove $GHDLFLAGS
ghdl synth $GHDLFLAGS -gCOUNTER_WIDTH=12 -gSTEP="$step" parser.vhd verifier.vhd top.vhd -e top > top_syn.vhd
ghdl synth $GHDLFLAGS -gCOUNTER_WIDTH=12 -gSTEP="$step" parser.vhd verifier.vhd top.vhd -e top > top_syn.vhd 2>/dev/null
ghdl analyze $GHDLFLAGS top_syn.vhd sim.vhd
ghdl elab-run $GHDLFLAGS sim -gSTEP="$step" --ieee-asserts=disable < "$INPUT"
done
done
else
ghdl remove $GHDLFLAGS
ghdl analyze $GHDLFLAGS parser.vhd verifier.vhd top.vhd sim.vhd
ghdl elab-run $GHDLFLAGS sim -gSTEP=1 < "$INPUT"
ghdl elab-run $GHDLFLAGS sim -gSTEP=2 < "$INPUT"
fi