day2/vhdl: don't simulate synthesized design by default
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6bcb64280d
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1 changed files with 13 additions and 12 deletions
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@ -3,20 +3,21 @@
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set -eu
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set -eu
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INPUT=$1
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INPUT=$1
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MODE=${2:-}
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GHDLFLAGS="--std=08 --workdir=workdir"
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GHDLFLAGS="--std=08 --workdir=workdir"
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mkdir -p workdir
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mkdir -p workdir
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if [[ $MODE = "--synth" ]]; then
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for step in 1 2; do
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ghdl remove $GHDLFLAGS
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ghdl synth $GHDLFLAGS -gCOUNTER_WIDTH=12 -gSTEP="$step" parser.vhd verifier.vhd top.vhd -e top > top_syn.vhd 2>/dev/null
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ghdl analyze $GHDLFLAGS top_syn.vhd sim.vhd
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ghdl elab-run $GHDLFLAGS sim -gSTEP="$step" --ieee-asserts=disable < "$INPUT"
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done
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else
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ghdl remove $GHDLFLAGS
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ghdl remove $GHDLFLAGS
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ghdl analyze $GHDLFLAGS parser.vhd verifier.vhd top.vhd sim.vhd
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ghdl analyze $GHDLFLAGS parser.vhd verifier.vhd top.vhd sim.vhd
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ghdl elab-run $GHDLFLAGS sim -gSTEP=1 < "$INPUT"
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ghdl elab-run $GHDLFLAGS sim -gSTEP=1 < "$INPUT"
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ghdl elab-run $GHDLFLAGS sim -gSTEP=2 < "$INPUT"
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ghdl elab-run $GHDLFLAGS sim -gSTEP=2 < "$INPUT"
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fi
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echo "Synthesized: "
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for step in 1 2; do
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ghdl remove $GHDLFLAGS
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ghdl synth $GHDLFLAGS -gCOUNTER_WIDTH=12 -gSTEP="$step" parser.vhd verifier.vhd top.vhd -e top > top_syn.vhd
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ghdl analyze $GHDLFLAGS top_syn.vhd sim.vhd
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ghdl elab-run $GHDLFLAGS sim -gSTEP="$step" --ieee-asserts=disable < "$INPUT"
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done
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