common: add VHDL testbench and runner

This commit is contained in:
Xiretza 2021-12-01 13:58:49 +01:00
parent dbcf8fa588
commit d60b8c5371
4 changed files with 37 additions and 24 deletions

View file

@ -1,27 +1,8 @@
#!/usr/bin/bash #!/bin/bash
set -eu source "$COMMON_DIR/vhdl_run.sh"
INPUT=$(readlink --canonicalize-existing "$1")
MODE=${2:-}
workdir=workdir
GHDLFLAGS="--std=08 --workdir=$workdir"
cd "$(dirname "${BASH_SOURCE[0]}")" cd "$(dirname "${BASH_SOURCE[0]}")"
mkdir -p workdir DUT_OUTPUT_WIDTH=12
test_synth day2 parser.vhdl verifier.vhdl top.vhdl
if [[ $MODE = "--synth" ]]; then
for step in 1 2; do
ghdl remove $GHDLFLAGS
ghdl synth $GHDLFLAGS -gCOUNTER_WIDTH=12 -gSTEP="$step" parser.vhd verifier.vhd top.vhd -e top > top_syn.vhd 2>/dev/null
ghdl analyze $GHDLFLAGS top_syn.vhd sim.vhd day2.vhdl
ghdl elab-run $GHDLFLAGS day2 -gSTEP="$step" --wave="$workdir/synth$step.ghw" --ieee-asserts=disable < "$INPUT"
done
else
ghdl remove $GHDLFLAGS
ghdl analyze $GHDLFLAGS parser.vhd verifier.vhd top.vhd sim.vhd day2.vhd
for step in 1 2; do
ghdl elab-run $GHDLFLAGS day2 -gSTEP="$step" --wave="$workdir/sim$step.ghw" < "$INPUT"
done
fi

View file

@ -6,7 +6,7 @@ use std.textio.all;
entity sim is entity sim is
generic ( generic (
OUTPUT_WIDTH : positive := 12; OUTPUT_WIDTH : positive;
STEP : natural range 1 to 2 STEP : natural range 1 to 2
); );
end entity; end entity;

30
common/vhdl_run.sh Executable file
View file

@ -0,0 +1,30 @@
#!/usr/bin/bash
set -euo pipefail
INPUT=$(readlink --canonicalize-existing "$1")
workdir=workdir
GHDLFLAGS="--std=08 --workdir=$workdir"
mkdir -p workdir
test_synth() {
local config_name=$1; shift
for step in 1 2; do
ghdl remove $GHDLFLAGS
ghdl synth $GHDLFLAGS -gOUTPUT_WIDTH="$DUT_OUTPUT_WIDTH" -gSTEP="$step" "$@" -e top > "$workdir/top_syn.vhdl" 2>/dev/null
ghdl analyze $GHDLFLAGS "$workdir/top_syn.vhdl" "$COMMON_DIR/testbench.vhdl" "$config_name.vhdl"
ghdl elab-run $GHDLFLAGS "$config_name" -gOUTPUT_WIDTH="$DUT_OUTPUT_WIDTH" --wave="$workdir/synth$step.ghw" --ieee-asserts=disable < "$INPUT"
done
}
test_sim() {
local config_name=$1; shift
ghdl remove $GHDLFLAGS
ghdl analyze $GHDLFLAGS "$COMMON_DIR/testbench.vhdl" "$@" "$config_name.vhdl"
for step in 1 2; do
ghdl elab-run $GHDLFLAGS "$config_name" -gOUTPUT_WIDTH="$DUT_OUTPUT_WIDTH" -gSTEP="$step" --wave="$workdir/sim$step.ghw" < "$INPUT"
done
}

View file

@ -6,6 +6,8 @@ cd "$(dirname "${BASH_SOURCE[0]}")"
YEAR=2020 YEAR=2020
export COMMON_DIR="$(realpath common)"
run_solution() { run_solution() {
if [ -d "$solution" ]; then if [ -d "$solution" ]; then
if [ -f "$solution/Cargo.toml" ]; then if [ -f "$solution/Cargo.toml" ]; then