2020 day2/vhdl: update to split out runner, handle line feeds
This commit is contained in:
parent
ab5fda541c
commit
cabc7f314d
8 changed files with 112 additions and 75 deletions
2
2020/day2/vhdl/.gitignore
vendored
2
2020/day2/vhdl/.gitignore
vendored
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@ -1,5 +1,5 @@
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workdir/
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*.o
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*.ghw
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sim
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day2
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top_syn.vhd
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16
2020/day2/vhdl/day2.vhd
Normal file
16
2020/day2/vhdl/day2.vhd
Normal file
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@ -0,0 +1,16 @@
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configuration day2 of sim is
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for aoc_stdio
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for dut_inst: dut
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use entity work.top port map (
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clk => clk,
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reset => reset,
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char => char,
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input_valid => input_valid,
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num_verified => output,
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output_valid => output_valid
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);
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end for;
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end for;
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end configuration;
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@ -5,10 +5,12 @@ entity parser is
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port (
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clk : in std_logic;
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reset : in std_logic;
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is_record : in std_logic;
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is_data : out std_logic;
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record_end : out std_logic;
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char : in character;
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input_valid : in std_logic;
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num1, num2 : out natural range 0 to 99;
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letter : out character
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@ -43,22 +45,22 @@ begin
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process(clk)
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begin
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if rising_edge(clk) then
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record_end <= '0';
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if reset then
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prev_digit <= 0;
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state <= S_NUM1;
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else
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elsif input_valid then
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prev_digit <= 0;
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case state is
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when S_NUM1 =>
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if is_record then
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if char = '-' then
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state <= S_NUM2;
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else
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num1 <= complete_num;
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prev_digit <= current_digit;
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end if;
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end if;
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when S_NUM2 =>
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if char = ' ' then
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state <= S_LETTER;
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@ -74,8 +76,9 @@ begin
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when S_END_SPACE =>
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state <= S_DATA;
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when S_DATA =>
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if not is_record then
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if char = LF then
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state <= S_NUM1;
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record_end <= '1';
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end if;
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end case;
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end if;
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@ -4,7 +4,8 @@ set -eu
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INPUT=$(readlink --canonicalize-existing "$1")
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MODE=${2:-}
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GHDLFLAGS="--std=08 --workdir=workdir"
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workdir=workdir
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GHDLFLAGS="--std=08 --workdir=$workdir"
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cd "$(dirname "${BASH_SOURCE[0]}")"
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@ -14,12 +15,13 @@ if [[ $MODE = "--synth" ]]; then
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for step in 1 2; do
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ghdl remove $GHDLFLAGS
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ghdl synth $GHDLFLAGS -gCOUNTER_WIDTH=12 -gSTEP="$step" parser.vhd verifier.vhd top.vhd -e top > top_syn.vhd 2>/dev/null
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ghdl analyze $GHDLFLAGS top_syn.vhd sim.vhd
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ghdl elab-run $GHDLFLAGS sim -gSTEP="$step" --ieee-asserts=disable < "$INPUT"
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ghdl analyze $GHDLFLAGS top_syn.vhd sim.vhd day2.vhdl
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ghdl elab-run $GHDLFLAGS day2 -gSTEP="$step" --wave="$workdir/synth$step.ghw" --ieee-asserts=disable < "$INPUT"
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done
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else
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ghdl remove $GHDLFLAGS
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ghdl analyze $GHDLFLAGS parser.vhd verifier.vhd top.vhd sim.vhd
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ghdl elab-run $GHDLFLAGS sim -gSTEP=1 < "$INPUT"
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ghdl elab-run $GHDLFLAGS sim -gSTEP=2 < "$INPUT"
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ghdl analyze $GHDLFLAGS parser.vhd verifier.vhd top.vhd sim.vhd day2.vhd
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for step in 1 2; do
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ghdl elab-run $GHDLFLAGS day2 -gSTEP="$step" --wave="$workdir/sim$step.ghw" < "$INPUT"
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done
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fi
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@ -1,15 +1,15 @@
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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
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[*] Wed Dec 2 10:02:23 2020
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[*] GTKWave Analyzer v3.3.109 (w)1999-2020 BSI
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[*] Wed Dec 1 11:30:36 2021
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[*]
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[dumpfile] "/home/xiretza/dev/aoc2020/day2/sim.ghw"
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[dumpfile_mtime] "Wed Dec 2 10:01:08 2020"
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[dumpfile_size] 410436
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[savefile] "/home/xiretza/dev/aoc2020/day2/sim.gtkw"
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[timestart] 410945000000
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[size] 1600 853
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[dumpfile] "/home/xiretza/dev/advent-of-code/2020/day2/vhdl/workdir/sim1.ghw"
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[dumpfile_mtime] "Wed Dec 1 11:29:37 2021"
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[dumpfile_size] 408417
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[savefile] "/home/xiretza/dev/advent-of-code/2020/day2/vhdl/sim.gtkw"
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[timestart] 411833500000
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[size] 1920 1035
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[pos] -1 -1
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*-27.864407 226600000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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*-25.864407 520000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] top.
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[treeopen] top.sim.
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[treeopen] top.sim.top.
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@ -20,9 +20,10 @@
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@28
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top.sim.clk
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top.sim.reset
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top.sim.top.parser_inst.is_record
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@420
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top.sim.top.char
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@28
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top.sim.input_valid
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@200
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-
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@28
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@ -33,15 +34,13 @@ top.sim.top.num2
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top.sim.top.letter
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@200
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-
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@420
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top.sim.top.verifier_inst.count
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@29
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top.sim.top.record_end
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@28
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top.sim.top.verifier_inst.verified
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top.sim.top.verified
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@200
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-
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@24
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#{top.sim.num_verified[11:0]} top.sim.num_verified[11] top.sim.num_verified[10] top.sim.num_verified[9] top.sim.num_verified[8] top.sim.num_verified[7] top.sim.num_verified[6] top.sim.num_verified[5] top.sim.num_verified[4] top.sim.num_verified[3] top.sim.num_verified[2] top.sim.num_verified[1] top.sim.num_verified[0]
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@29
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top.sim.top.record_ended
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[pattern_trace] 1
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[pattern_trace] 0
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@ -6,25 +6,44 @@ use std.textio.all;
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entity sim is
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generic (
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COUNTER_WIDTH : positive := 12;
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OUTPUT_WIDTH : positive := 12;
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STEP : natural range 1 to 2
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);
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end entity;
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architecture a of sim is
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architecture aoc_stdio of sim is
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type char_file_t is file of character;
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file stdin : char_file_t open READ_MODE is "STD_INPUT";
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signal char_in : character;
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signal clk, reset, is_record : std_logic;
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signal num_verified : unsigned(COUNTER_WIDTH-1 downto 0);
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signal clk, reset, input_valid, output_valid : std_logic;
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signal output : unsigned(OUTPUT_WIDTH-1 downto 0);
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procedure print(s: string) is
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variable l : line;
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begin
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write(l, s);
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writeline(output, l);
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writeline(std.textio.output, l);
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end procedure;
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component dut is
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generic (
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OUTPUT_WIDTH : positive;
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STEP : natural range 1 to 2
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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char : in character;
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input_valid : in std_logic;
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output : out unsigned(OUTPUT_WIDTH-1 downto 0);
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output_valid : out std_logic
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);
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end component;
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begin
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process
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variable current_line : line;
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variable current_char : character;
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variable good : boolean;
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@ -38,7 +57,7 @@ begin
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end procedure;
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begin
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clk <= '0';
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is_record <= '0';
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input_valid <= '0';
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char_in <= NUL;
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reset <= '1';
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@ -46,41 +65,36 @@ begin
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reset <= '0';
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cycle_clock;
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lines_loop: loop
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exit lines_loop when endfile(input);
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readline(input, current_line);
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input_valid <= '1';
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is_record <= '1';
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chars_loop: loop
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read(current_line, current_char, good);
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exit chars_loop when not good;
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chars_loop: while not endfile(stdin) loop
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read(stdin, current_char);
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char_in <= current_char;
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cycle_clock;
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end loop;
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is_record <= '0';
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input_valid <= '0';
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cycle_clock;
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end loop;
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cycle_clock;
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print(to_string(to_integer(num_verified)));
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assert output_valid report "Output was not valid at end of simulation" severity failure;
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print(to_string(to_integer(output)));
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wait;
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end process;
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top: entity work.top
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dut_inst: dut
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generic map (
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COUNTER_WIDTH => COUNTER_WIDTH,
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OUTPUT_WIDTH => OUTPUT_WIDTH,
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STEP => STEP
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)
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port map (
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clk => clk,
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reset => reset,
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char => char_in,
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is_record => is_record,
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num_verified => num_verified
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input_valid => input_valid,
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output => output,
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output_valid => output_valid
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);
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end architecture;
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@ -4,15 +4,18 @@ use ieee.std_logic_1164.all,
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entity top is
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generic (
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COUNTER_WIDTH : positive;
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OUTPUT_WIDTH : positive;
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STEP : natural range 1 to 2
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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char : in character;
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is_record : in std_logic;
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num_verified : out unsigned(COUNTER_WIDTH-1 downto 0)
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input_valid : in std_logic;
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num_verified : out unsigned(OUTPUT_WIDTH-1 downto 0) := (others => '0');
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output_valid : out std_logic
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);
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end entity;
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@ -21,20 +24,20 @@ architecture behaviour of top is
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signal num1, num2 : natural range 0 to 99;
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signal letter : character;
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signal prev_is_record : std_logic;
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signal record_ended : std_logic;
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signal record_end : std_logic;
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signal verified : std_logic;
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begin
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record_ended <= prev_is_record and not is_record;
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parser_inst: entity work.parser
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port map (
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clk => clk,
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reset => reset,
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is_record => is_record,
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record_end => record_end,
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is_data => is_data,
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char => char,
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input_valid => input_valid,
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num1 => num1,
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num2 => num2,
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@ -45,8 +48,8 @@ begin
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verifier_inst: entity work.verifier(step1)
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port map (
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clk => clk,
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reset => reset or record_ended,
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is_data => is_data,
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reset => reset or record_end,
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enable => is_data and input_valid,
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num1 => num1,
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num2 => num2,
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letter => letter,
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@ -57,8 +60,8 @@ begin
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verifier_inst: entity work.verifier(step2)
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port map (
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clk => clk,
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reset => reset or record_ended,
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is_data => is_data,
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reset => reset or record_end,
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enable => is_data and input_valid,
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num1 => num1,
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num2 => num2,
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letter => letter,
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@ -72,13 +75,13 @@ begin
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process(clk)
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begin
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if rising_edge(clk) then
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prev_is_record <= is_record;
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if reset then
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prev_is_record <= '0';
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num_verified <= (others => '0');
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elsif record_ended and verified then
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elsif record_end and verified then
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num_verified <= num_verified + 1;
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end if;
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end if;
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end process;
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output_valid <= '1';
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end architecture;
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@ -5,7 +5,7 @@ entity verifier is
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port (
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clk : in std_logic;
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reset : in std_logic;
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is_data : in std_logic;
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enable : in std_logic;
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num1, num2 : in natural range 0 to 99;
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letter : in character;
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@ -24,7 +24,7 @@ begin
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if rising_edge(clk) then
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if reset then
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count <= 0;
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elsif is_data then
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elsif enable then
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if char = letter then
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count <= count + 1;
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end if;
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@ -45,7 +45,7 @@ begin
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if reset then
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count <= 1;
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parity <= '0';
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elsif is_data then
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elsif enable then
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count <= count + 1;
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if (count = num1 or count = num2) and char = letter then
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parity <= not parity;
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