2020 day2/vhdl: split off util package

2020/day2/vhdl/parser.vhdl

@@ -1,6 +1,8 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
+use work.util.all;
+
 entity parser is
 	port (
 		clk : in std_logic;
@@ -21,23 +23,13 @@ architecture behaviour of parser is
 	type state_t is (S_NUM1, S_NUM2, S_LETTER, S_COLON, S_END_SPACE, S_DATA);
 	signal state : state_t := S_NUM1;
 
-	subtype digit is natural range 0 to 9;
+	type multiples_lookup_t is array(digit_t) of natural range 0 to 90;
-	type multiples_lookup_t is array(digit) of natural range 0 to 90;
 	constant TEN_MULTIPLES : multiples_lookup_t := (0, 10, 20, 30, 40, 50, 60, 70, 80, 90);
 
 	-- most significant digit of number
-	signal prev_digit : digit := 0;
+	signal prev_digit : digit_t := 0;
-	signal current_digit : digit;
+	signal current_digit : digit_t;
 	signal complete_num : natural range 0 to 99;
-
-	function char_to_digit(input : in character) return digit is
-	begin
-		if input >= '0' and input <= '9' then
-			return character'pos(input) - character'pos('0');
-		else
-			return 0;
-		end if;
-	end function;
 begin
 	current_digit <= char_to_digit(char);
 	complete_num <= TEN_MULTIPLES(prev_digit) + current_digit;

common/util.vhdl

@@ -0,0 +1,15 @@
+package util is
+	subtype digit_t is natural range 0 to 9;
+	function char_to_digit(input : in character) return digit_t;
+end package;
+
+package body util is
+	function char_to_digit(input : in character) return digit_t is
+	begin
+		if input >= '0' and input <= '9' then
+			return character'pos(input) - character'pos('0');
+		else
+			return 0;
+		end if;
+	end function;
+end package body;

common/vhdl_run.sh

@@ -13,7 +13,7 @@ test_synth() {
 
 	for step in 1 2; do
 		ghdl remove $GHDLFLAGS
-		ghdl synth $GHDLFLAGS -gOUTPUT_WIDTH="$DUT_OUTPUT_WIDTH" -gSTEP="$step" "$@" -e top > "$workdir/top_syn.vhdl" 2>/dev/null
+		ghdl synth $GHDLFLAGS -gOUTPUT_WIDTH="$DUT_OUTPUT_WIDTH" -gSTEP="$step" "$COMMON_DIR/util.vhdl" "$@" -e top > "$workdir/top_syn.vhdl" 2>/dev/null
 		ghdl analyze $GHDLFLAGS "$workdir/top_syn.vhdl" "$COMMON_DIR/testbench.vhdl" "$config_name.vhdl"
 		ghdl elab-run $GHDLFLAGS "$config_name" -gOUTPUT_WIDTH="$DUT_OUTPUT_WIDTH" --wave="$workdir/synth$step.ghw" --ieee-asserts=disable < "$INPUT"
 	done
@@ -23,7 +23,7 @@ test_sim() {
 	local config_name=$1; shift
 
 	ghdl remove $GHDLFLAGS
-	ghdl analyze $GHDLFLAGS "$COMMON_DIR/testbench.vhdl" "$@" "$config_name.vhdl"
+	ghdl analyze $GHDLFLAGS "$COMMON_DIR/testbench.vhdl" "$COMMON_DIR/util.vhdl" "$@" "$config_name.vhdl"
 	for step in 1 2; do
 		ghdl elab-run $GHDLFLAGS "$config_name" -gOUTPUT_WIDTH="$DUT_OUTPUT_WIDTH" -gSTEP="$step" --wave="$workdir/sim$step.ghw" < "$INPUT"
 	done