dipl/code/dac/saw_fifo_backplane/src/main.c
Tyrolyean a78cc80bb2
Added stuff from corona start
Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
2020-03-14 22:30:05 +01:00

152 lines
3.1 KiB
C

/* Copyright © 2020 tyrolyean
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#define F_CPU 16000000UL
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <avr/wdt.h>
#include <util/delay.h>
#include <avr/interrupt.h>
#define BUS_HOLD_US 1
/* Shift values inside the PORTK Register */
#define WR_SHIFT 1
#define RD_SHIFT 2
#define MR_SHIFT 0
#define CS_SHIFT 4
uint8_t mcusr_mirror __attribute__ ((section (".noinit")));
void get_mcusr(void) \
__attribute__((naked)) \
__attribute__((section(".init3")));
void get_mcusr(void)
{
mcusr_mirror = MCUSR;
MCUSR = 0;
wdt_disable();
}
void set_addr(uint8_t addr){
PORTK = addr;
return;
}
uint8_t sine_table[256];
void write_to_dac(uint8_t addr, uint8_t data){
set_addr(addr);
DDRF = 0xFF;
PORTL &= ~(1<<WR_SHIFT);
PORTF = data;
PORTL &= ~(1<<CS_SHIFT);
_delay_us(BUS_HOLD_US); /*Wait for the data and signal lanes to become stable*/
PORTL |= 1<<CS_SHIFT;
set_addr(0x00);
PORTL |= 1<<WR_SHIFT;
PORTF = 0x00;
return;
}
uint8_t read_from_dac(uint8_t addr){
uint8_t data = 0x00;
set_addr(addr);
DDRF = 0x00;
PORTF = 0x00;
PORTL &= ~(1<<RD_SHIFT);
PORTL &= ~(1<<CS_SHIFT);
_delay_us(BUS_HOLD_US); /* Wait for the data and signal lanes to become stable*/
data = PINF;
PORTL |= 1<<CS_SHIFT;
set_addr(0x00);
PORTL |= 1<<RD_SHIFT;
DDRF = 0xFF;
PORTF = 0x00;
_delay_us(BUS_HOLD_US); /*Wait for the data and signal lanes to become stable*/
return data;
}
int routine();
int main(){
/* Disable interrupts during initialisation phase */
cli();
/* Setup Data Direction Registers and populate with sane default
values */
DDRF = 0xFF; /* Data Bus */
DDRK = 0xFF; /* Address Bus */
DDRL = 0xFF; /* Control Bus */
PORTF = 0x00;
PORTK = 0x00;
PORTL = 0x00;
/* Cleanly reset the dac uart */
PORTL |= (1<<WR_SHIFT);
PORTL |= (1<<RD_SHIFT);
PORTL |= (1<<CS_SHIFT);
PORTL |= (1<<MR_SHIFT);
_delay_us(100);
PORTL &= ~(1<<MR_SHIFT);
/* Generate sine table */
for(size_t i = 0; i < 256; i++){
sine_table[i] = 0xFF&((int)((sin(i/((double)255)*(3.141592*2))*127.5+127.5)));
}
sei();
/* Enable the hardware watchdog. In case the microcontroller fails to
* finish it's task within the specified time, the watchdog will reset
* the atmel cookie.
*/
wdt_enable(WDTO_1S);
while(1){
wdt_reset();
if(routine() < 0){
}
}
return 0;
}
int routine(){
for(uint8_t i = 0; i < 0xFF; i++){
write_to_dac(i%2, sine_table[i]);
}
write_to_dac(0x00, 0x00);
write_to_dac(0x01, 0x00);
_delay_ms(10);
return 0;
}