18 lines
No EOL
386 B
VHDL
18 lines
No EOL
386 B
VHDL
entity alu is
|
|
port (
|
|
clk : in std_logic;
|
|
|
|
enable_math : in std_logic;
|
|
valid : out std_logic;
|
|
operation : in alu_operation_t;
|
|
a, b : in yarm_word;
|
|
math_result : out yarm_word;
|
|
|
|
-- compare inputs
|
|
-- do signed comparisons
|
|
enable_cmp : in std_logic;
|
|
cmp_signed : in std_logic;
|
|
cmp1, cmp2 : in yarm_word;
|
|
cmp_result : out compare_result_t
|
|
);
|
|
end alu; |