72 lines
1.1 KiB
VHDL
72 lines
1.1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity counter_tb is
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end counter_tb;
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architecture test of counter_tb is
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signal clk, reset, enable, direction : std_logic;
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signal s_count_out : std_logic_vector(7 downto 0);
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signal count_out : unsigned(7 downto 0);
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begin
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uut: entity work.counter
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port map (
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clk => clk,
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reset => reset,
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enable => enable,
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direction => direction,
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count_out => s_count_out
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);
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count_out <= unsigned(s_count_out);
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simulate: process
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begin
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clk <= '0';
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reset <= '1';
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enable <= '0';
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wait for 30 ns;
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assert count_out = 0;
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reset <= '0';
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clk <= '0';
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wait for 10 ns;
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clk <= '1';
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wait for 10 ns;
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assert count_out = 0;
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enable <= '1';
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direction <= '0';
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clk <= '0';
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wait for 10 ns;
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clk <= '1';
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wait for 10 ns;
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assert count_out = 255;
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direction <= '1';
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clk <= '0';
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wait for 10 ns;
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clk <= '1';
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wait for 10 ns;
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clk <= '0';
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wait for 10 ns;
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clk <= '1';
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wait for 10 ns;
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assert count_out = 1;
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wait for 30 ns;
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wait;
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end process;
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end test;
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