Tyrolyean 510a6149d1 Added corrections at last minute ... Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>		2020-03-31 23:45:03 +02:00
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Anhang	Added corrections at last minute	2020-03-31 23:45:03 +02:00
core	Added corrections at last minute	2020-03-31 23:45:03 +02:00
DP	Added corrections at last minute	2020-03-31 23:45:03 +02:00
soc	Move FPGA development section to separate file	2020-03-31 14:40:29 +02:00
vhdl_intro	Link to VHDL intro appendix	2020-03-30 20:54:36 +02:00
abstract.tex	Added corrections at last minute	2020-03-31 23:45:03 +02:00
fpga-development.tex	Added corrections at last minute	2020-03-31 23:45:03 +02:00
intro.tex	Added corrections at last minute	2020-03-31 23:45:03 +02:00
result.tex	Added corrections at last minute	2020-03-31 23:45:03 +02:00