377 lines
15 KiB
TeX
377 lines
15 KiB
TeX
\subsection{Audio Digital-Analog-Converter}
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A digital to analog converter takes a digital number and converts it to a
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analog signal. The output of such a conversion is called a sample. With
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enough samples per second various different waveforms can be produced, which,
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when amplified and put onto a speaker, can be heared by the human ear as a tone.
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With various tones in series a melody can be produced, which is what the DAC in
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this implementation does.
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\subsubsection{TLC 7528 Dual R2R Ladder DAC}
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The TLC 7528 is a Dual output parallel input R2R Ladder DAC with a maximum
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sample rate of 10MHz \cite{tlc7528}, and which (should be
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\footnote{See Figure \ref{fig:tlc7528_saw_nonlin}}) is monotonic over the
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entire D/A Conversion Range. The TLC-7528 is the only component chosen, where
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availability is not a factor, but rather it's design. It is the cheapest
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dual R2R Ladder DAC which takes \textbf{PARALLEL} input, which is an important
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feature, because the backbone of the project is its parallel bus. Further the
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DAC was developed for audio aplications\cite{tlc7528}, which made its use
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obvious. The TLC-7528 was the only IC available as DIP
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\footnote{DIP... Dual Inline Package}, of which the pinout can be seen in Figure
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\ref{fig:tlc7528_pinout}.
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\begin{figure}[H]
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\centering
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\includesvg[height=.3\textheight, angle=0]{pics/slas062e_pinout.svg}
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\caption{TLC-7528 Pinout\cite{tlc7528}}
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\label{fig:tlc7528_pinout}
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\end{figure}
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\subsubsection{IDT7201 CMOS FIFO Buffer}
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The IDT7201 is an asychronous CMOS FIFO. That means, that it can be read with
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a completely independant speed from which it is written and vice versa. It has
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9 bit words, which can be seen in Figure \ref{fig:idt7201_pinout}, and can
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store up to 256 words\cite{idt7201}. It is used as a buffer
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to store data describing the targeted waveform in order to free time on the
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parallel bus for interaction with the 16550 UART.
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\begin{figure}[H]
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\centering
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\includesvg[height=.3\textheight, angle=0]{pics/idt7201_pinout.svg}
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\caption{IDT-7201 Pinout\cite{idt7201}}
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\label{fig:idt7201_pinout}
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\end{figure}
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\subsubsection{Theory verfication}
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Before tests of the complete unit were conducted, the functionality of the
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device and the validity of the knowledge of operations were performed. For that
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the DAC was directly connected to the ATMega without the FIFO in front of it.
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A saw was generated on only the DACA channel, which was put into voltage mode
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as described in the datasheet\cite{tlc7528} and seen in Figure
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\ref{fig:tlc7528_volt}.
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After the result seen in Figure \ref{fig:tlc7528_saw_nonlin}
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was measured, a lot of effort was put in to determine the source of the heavy
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noise, however no obvious conclusions can be made, execpt that it comes from the
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DAC itself and is consistant over whatever frequency used. A damaged IC could be
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the reason or a sloppy production progress. Filters can be used to reduce the
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noise, however this was not done in this thesis, as the generated audio does
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not seem to suffer from these non-linearities as badly as when measured
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standalone.
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\begin{figure}[H]
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\centering
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\includesvg[height=.3\textheight, angle=0]{pics/slas062e_volt.svg}
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\caption{TLC-7528 in voltage modet\cite{tlc7528}}
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\label{fig:tlc7528_volt}
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\end{figure}
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\begin{figure}[H]
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\begin{tikzpicture}
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\begin{axis}[
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ylabel=REFA Voltage,
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xlabel=Time,
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grid=both,
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minor tick num=5,
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xmin=-2.030599999999999e-05,
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xmax=0.000598364,
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width=\textwidth,
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height=0.4\textheight]
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\addplot table [x=t, y=c1, col sep=comma, mark=none] {meas/20200210_saw_nonlin.csv};
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\end{axis}
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\end{tikzpicture}
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\caption{Measurement of a generated SAW signal via the TLC7528}
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\label{fig:tlc7528_saw_nonlin}
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\end{figure}
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\subsubsection{Schematics}
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Based on the descriptions in the datasheets the schematic in figure
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\ref{fig:schem_dac} was developed.
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\begin{figure}[H]
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\centering
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\includegraphics[height=.65\textheight, angle=-90]{schem_pdf/dac.pdf}
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\caption{The schematic of the DAC Module}
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\label{fig:schem_dac}
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\end{figure}
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\paragraph{Element Description}
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Diodes D1 through D4 are used as OR-Gates in conjunction with R1 and R2 to
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generate the $\lnot MODRD$ and $\lnot MODWR$ signals for the D Flip-Flop
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\footnote{74HC374\cite{74hc374}} and FIFO respectively by these formulas:
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$\lnot MODRD = \lnot RD \lor \lnot MS2$
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$\lnot MODWR = \lnot WR \lor \lnot MS2$
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On a read access the output enable of the D-Latch becomes low, which writes
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the status bits of the FIFO onto the data bus. C1, C2 and C3 are for stability
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reasons and are good practice similar to the UART module. 74HC00 is a quad
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NAND-Gate\cite{74hc00}, which is only used for inversion, chosen, like the
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74HC374, for availability reasons. The A part of the NAND-Gate inverts the $MR$
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signal from the bus to a $\lnot MR$ signal, as the FIFOs reset is low active.
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The B part of the NAND-Gate inverts the FIFO Empty flag. It's output is
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connected to the $\lnot WR$ input of the DAC, which means, that the DAC doesn't
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convert the input anymore, if the FIFO Empty flag is set to low.
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The NE555 generates the audio clock signal, which should be the double of
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44.1kHz\footnote{Because we have 2 output channels}, as 44.1kHz is the standard
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samling rate of CD-Audio\cite{iec60908} and 2 channels need to be sampled.
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Resistors R9 and R10 togehter with C7
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form the Oscillator part of the NE55. C4 is for stability reasons and doesn't
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define the frequency of the oscillator.
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The generated clock is used for the $\lnot RD$ of the FIFO and inverted on the
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DAC, which makes the data available on the output before being stored into the
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DAC, as it receives the signal to store the data, after the FIFO makes it
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available on the bus.
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The DAC is operated in voltage mode, as described in Figure \ref{fig:tlc7528_volt},
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with it's voltage source beeing available at either $3.472V_{pp}$ for
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professional
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audio or $0.894V_{pp}$ for consumer audio, as defined per convention.\cite{audiob}
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The voltage source can be controlled via Jumper JP1.
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C5 and C6 together with the load resistance on the audio jack form a high pass
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with a cutoff frequency of
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$f_C = \frac{1}{2\pi R C} = \frac{1}{2\times \pi\times 10K\Omega\times 100\mu F} = 0.159154943Hz$
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which should cover the hearable spectrum. The high pass was needed to generate
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a positive and negative half of the wave form, as the DC-Offset with a frequency
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of 0Hz is orders of magnitudes lower, than the $f_C$ of the highpass gets
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filtered away.
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R7 and R8 have been installed in order to unload the capacitors after device
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poweroff.
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\paragraph{Functional Description}
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On a read of the module the $\lnot MS2$ line goes low as well as the $\lnot RD$
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line, which combined by the as OR gate used diodes D1/D2 and resistor R1 forms
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the MODREAD
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signal. The modread signal is passed on to the $\lnot OE$ pin of the D-Flip-Flop
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which writes the FIFO status bits onto the data bus.
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On write the same or gate is formed with diodes D3/D4 and resistor R2 which
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combines signals $\lnot MS2$ and $\lnot WR$ into MODWRITE. MODWRITE is then fed
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into the $\lnot W$ pin of the FIFO which stores the data on the data bus into
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it's internal buffer.
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The FIFO is read with the clock generated by the NE555
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(see the NE555 paragraph below) which puts the data onto the bus between FIFO
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and DAC. The DAC reads the data into its internal buffer after the FIFO has put
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it onto the DATA lanes due to the inversion by the B part of the 74HC00 and the
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output beeing mapped to the $\lnot CS$ pin of the DAC. When
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the FIFO is empty it produces nonsense as output, to mittigate errors resulting
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from this the $\lnot EF$ output of the FIFO is inverted by the C part of the
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74HC00 and put onto the $\lnot WR$ pin of the DAC.
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The maximum amplitude can be selected by jumper JP1. Generated waveforms by the
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DAC are filtered against a DC offset via the highpasses built by C5/R7 and C6/R8
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respectively. The resulting waveform can be measured on audio jack J1.
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\paragraph{NE55 Clock Source}
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Though used as a clock source, the NE555 is a bad clock source, if a stable
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frequency is needed, because it varies widely with temperature, preasure and
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ageing
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elements. A better solution would have been a quartz, which is divided down to
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the desired frequency, which was what CD-Drives used to do, but more commonly in
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modern CD Drives, an ASIC
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\footnote{ASIC...Application-specific integrated circuit}
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with an internal PLL is used, thus the required quartz can no longer be sourced
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via conventional electronic resellers.
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\subsubsection{DAC Module Read}
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On a read the status bits of the FIFO, which has been latched into the 74HC374
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D-Flip-Flop, are written onto the Data bus. Table \ref{tab:dac_data} defines the
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layout of these status bits on the data bus.
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\begin{table}[H]
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\centering
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\begin{tabular}{| c | r |}
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\hline
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\textbf{Bit position} & \textbf{Usage}\\
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\hline
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\hline
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0 & FIFO empty flag \\
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\hline
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1 & Not used (originally FIFO low)\\
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\hline
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2 & FIFO half full\\
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\hline
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3 & FIFO full \\
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\hline
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4 & Not used\\
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\hline
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5 & Not used\\
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\hline
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6 & Not used\\
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\hline
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7 & Not used\\
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\hline
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\end{tabular}
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\caption{The layout of the Data Bus on DAC read}
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\label{tab:dac_data}
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\end{table}
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\subsubsection{Demonstration Software}
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\paragraph{SAW Generator}
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To prove that read and write access from the D Flip-Flop and the FIFO are
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working,
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the same saw signal has been generated as in figure \ref{fig:tlc7528_saw_nonlin}
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, however the signal was put into the FIFO and not the DAC directly. The
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resulting saw wave can be seen in figure \ref{fig:tlc7528_saw_fifo} together
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with the FIFO Empty flag. The FIFO Empty flag, as explained before, is inverted
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and starts/ends the complete D/A conversion, until further data is received.
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\begin{figure}[H]
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\begin{tikzpicture}
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\begin{axis}[
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ylabel=REFA Voltage,
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xlabel=Time,
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grid=both,
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minor tick num=5,
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xmin=0.02023862769230769,
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xmax=0.02642198769230769,
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width=\textwidth,
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height=0.4\textheight]
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\addplot table [x=t, y=c1, col sep=comma, mark=none] {meas/20200308fifo_44_1_saw_withfifoempty.csv};
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\addplot table [x=t, y=c2, col sep=comma, mark=none] {meas/20200308fifo_44_1_saw_withfifoempty.csv};
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\legend{REFA,$\lnot EF$}
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\end{axis}
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\end{tikzpicture}
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\caption{Measurement of a generated SAW signal with the FIFO Empty flag}
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\label{fig:tlc7528_saw_fifo}
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\end{figure}
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The time difference betwen a store and complete write cycle can be seen in figure
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\ref{fig:fifo_dac_store}, while figure \ref{fig:fifo_dac} shows the
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transmission between dac and fifo in more detail.
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\begin{figure}[H]
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\centering
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\includegraphics[width=\textwidth, angle=0]{meas/20200308fifo_44_1_cnt.png}
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\caption{A transmission between the FIFO and the DAC}
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\label{fig:fifo_dac}
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\end{figure}
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\begin{figure}[H]
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\centering
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\includegraphics[width=\textwidth, angle=0]{meas/20200308fifo_44_1_saw.png}
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\caption{A fifo store operation in contrast to the load operation}
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\label{fig:fifo_dac_store}
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\end{figure}
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The initialisation routines and read/write operations for the DAC module are
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basically the same as for the UART module, and have thus been ommitted. They
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can be seen in listing \ref{lst:16550-transmit}.
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\lstinputlisting[language=C,frame=trBL,
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breaklines=true, breakautoindent=true, formfeed=\newpage,
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label={lst:dac_saw}, caption={SAW Generation for the DAC with FIFO},
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style=cstyle, firstline=134, lastline=144]
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{code/dac/saw_fifo_backplane/src/main.c}
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\paragraph{Sine Generator}
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As a further example a sine was generated and played on the DAC. The ATMega
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itself is not powerful enough to generate the sine on the fly, therefore a
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lookup-table had to be generated, which can be seen in listing
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\ref{lst:dac_sine_lut}. How the data is transmitted to the FIFO can be seen
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in listing \ref{lst:dac_sine} and figure \ref{fig:fifo_sine_store}, and the
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resulting sine on both output channels can be seen in figure
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\ref{fig:sine_dacab}.
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\lstinputlisting[language=C,frame=trBL,
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breaklines=true, breakautoindent=true, formfeed=\newpage,
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label={lst:dac_sine_lut}, caption={Sine LUT Generation},
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style=cstyle, firstline=118, lastline=123]
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{code/dac/sine_fifo_backplane/src/main.c}
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The look-up table has a size of 256, which is the maximum value an 8 bit integer
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can take. This size was chosen to make operation faster as it only takes
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one cycle to load an array value into a register and another one to store it
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into the GPIO register. The sine table in further examples was pre-genrated on
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the compiling host to reduce startup time. The method shown in listing
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\ref{lst:dac_sine_lut} is not fast due to the lack of a floating point unit
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on the AVR. \cite{atmega2560}
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\lstinputlisting[language=C,frame=trBL,
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breaklines=true, breakautoindent=true, formfeed=\newpage,
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label={lst:dac_sine}, caption={DAC Sine Generation},
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style=cstyle, firstline=141, lastline=152]
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{code/dac/sine_fifo_backplane/src/main.c}
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\begin{figure}[H]
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\centering
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\includegraphics[width=\textwidth, angle=0]{meas/20200310sine_dac.png}
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\caption{Storage and retrieval of a sine to and from the FIFO}
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\label{fig:fifo_sine_store}
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\end{figure}
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\begin{figure}[H]
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\begin{tikzpicture}
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\begin{axis}[
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ylabel=Channel Voltage,
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xlabel=Time,
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grid=both,
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minor tick num=5,
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xmin=-0.001746707777777778,
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xmax=0.001774992222222222,
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width=\textwidth,
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height=0.4\textheight]
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\addplot table [x=t, y=c1, col sep=comma, mark=none] {meas/20200310sine_dac_osz.csv};
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\addplot table [x=t, y=c2, col sep=comma, mark=none] {meas/20200310sine_dac_osz.csv};
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\legend{DACA,DACB}
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\end{axis}
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\end{tikzpicture}
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\caption{Measuremet of the generated sine from the sine LUT on DACA and DACB}
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\label{fig:sine_dacab}
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\end{figure}
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\subsubsection{Addressing DACA and DACB}
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The DAC used has 2 output channels, which can be selected by the
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$\lnot DACA/DACB$ pin as seen in figure \ref{fig:tlc7528_pinout}. This pin was
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mapped to bit 0 of the address bus in order to make use of it. Bit 8 on the fifo
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was used to store the bit. It is not implemented with half the bus clock to
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make both channels independent of each other. This however uses more time on the
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backend because it means the FIFO is used up at twice the speed. No current
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example makes use of this, but it may be used in future examples and
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implementations on this unit.
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On the audio jack DACA is mapped to the right channel and DACB to the left
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channel.
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\subsubsection{Final Module}
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The final module can be seen in figure \ref{fig:dac_mod} with, from bottom to
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top, the 74HC374 D-Flip-Flop, the IDT-7201 FIFO, the 74HC00 NAND-Gates, the
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TLC-7528 DAC and the NE555 oszillator. The jumper on the left is the voltage
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select and the jumper on the right the clock select. The two pin headers on the
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top have been installed for voltage measurement on the left and right audio
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channels while the audio jack is in use.
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\begin{figure}[H]
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\centering
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\includegraphics[width=\textwidth, angle=90]{pics/dac}
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\caption{The final DAC module}
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\label{fig:dac_mod}
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\end{figure}
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