33 lines
666 B
VHDL
33 lines
666 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity counter is
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port (
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clk : in std_logic;
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reset : in std_logic;
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enable : in std_logic;
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direction : in std_logic;
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count_out : out std_logic_vector(7 downto 0)
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);
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end counter;
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architecture behaviour of counter is
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signal count : unsigned(7 downto 0) := (others => '0');
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begin
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proc: process(clk)
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begin
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if reset then
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count <= (others => '0');
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elsif rising_edge(clk) and enable = '1' then
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if direction = '1' then
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count <= count + 1;
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else
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count <= count - 1;
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end if;
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end if;
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end process;
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count_out <= std_logic_vector(count);
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end behaviour;
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