library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter_tb is
end counter_tb;

architecture test of counter_tb is
	signal clk, reset, enable, direction : std_logic;
	signal s_count_out : std_logic_vector(7 downto 0);

	signal count_out : unsigned(7 downto 0);
begin
	uut: entity work.counter
		port map (
			clk       => clk,
			reset     => reset,
			enable    => enable,
			direction => direction,

			count_out => s_count_out
		);

	count_out <= unsigned(s_count_out);

	simulate: process
		begin
			clk <= '0';
			reset <= '1';
			enable <= '0';

			wait for 30 ns;
			assert count_out = 0;

			reset <= '0';

			clk <= '0';
			wait for 10 ns;
			clk <= '1';
			wait for 10 ns;

			assert count_out = 0;

			enable <= '1';
			direction <= '0';

			clk <= '0';
			wait for 10 ns;
			clk <= '1';
			wait for 10 ns;

			assert count_out = 255;

			direction <= '1';

			clk <= '0';
			wait for 10 ns;
			clk <= '1';
			wait for 10 ns;

			clk <= '0';
			wait for 10 ns;
			clk <= '1';
			wait for 10 ns;

			assert count_out = 1;

			wait for 30 ns;
			wait;
		end process;
end test;