library ieee;
use ieee.std_logic_1164.all;

entity flipflop_tb is
end entity;

architecture test of flipflop_tb is
	signal s_d, s_e, s_q : std_logic;
begin
	uut: entity work.flipflop
		port map (
			d => s_d,
			e => s_e,
			q => s_q
		);

	simulate: process
		begin
			s_d <= '0';
			s_e <= '0';

			wait for 100 ns;

			s_e <= '1';
			wait for 10 ns;
			s_e <= '0';

			assert s_q = '0';

			wait for 50 ns;
			s_d <= '1';
			wait for 50 ns;

			assert s_q = '0';

			s_e <= '1';
			wait for 10 ns;
			s_e <= '0';
			assert s_q = '1';

			wait for 100 ns;
			wait;
		end process;
end architecture;