\subsection{Parallel bus}

The core part of the hardware is the interface between the microprocessor and
the hardware peripherials. This bus is delivering data in parallel and is
therefore named the ``parallel bus``.  This bus has 3 different sub-parts:

\begin{enumerate}
	\item{The address bus}
	\item{The data bus}
	\item{The control bus}
\end{enumerate}

This split is common in many computer architectures and bus systems used by
various microprocessor manufacturers. In figure \ref{fig:atari_pbi} the
layout of the Atari Parallel Bus Interface is shown as used on the Atari 800XL.

\begin{figure}[H]
	\includegraphics[width=\textwidth, angle=0]{pics/atari_pbi}
	\caption{Atari PBI Pinout;Source: \url{https://www.atarimagazines.com}}
	\label{fig:atari_pbi}
\end{figure}

\paragraph{System Bus}

In some architectures the backbone parallel bus consisting of data- address- and
control bus is called the system bus. The system bus even has its own wikipedia
article \footnote{\url{https://en.wikipedia.org/wiki/System_bus}} and the 
picture seen in
figure \ref{fig:sysbus}, which has been taken from this wikipedia article, even
shows the exact same parts. However the origin of this term could not be
determined and its use was the most common when describing the interface between
the fabric of the CPU with external parts via this interface on a motherboard,
which ran on system clock speed and was synchronized with the processor.
The term parallel bus was chosen for this thesis because the bus runs on an 
independant clock speed and only interacts with the processor asynchronous to
its clock. The term front side bus would be more fitting but not used because of
its affiliation with intel products.

\begin{figure}[H]
	\includesvg[width=\textwidth, angle=0]{pics/sysbus}
	\caption{System bus structural diagram; Source: \url{https://en.wikipedia.org/}}
	\label{fig:sysbus}
\end{figure}


\subsubsection{Address Bus}

The address bus contains the nescessary data lines for addressing the individual
registers of the Serial connection and the UART. On any modern system this bus
is from 16 to 64 bits wide. For our implementation the bus size was chosen to
be 8 bit, which is multiple times the amount of needed address space, but 
is the smallest addressable unit on most microcontroller architectures and
therefore easy to program with. The address bus is unidirectional.

\subsubsection{Data Bus}

The data bus contains the actual data to be stored to and read from registers.
The data bus is, as well on most systems a multiple of 16 bits wide, but for the
same reasons as the data bus, was shrunk down in our case to 8 bits. The data
bus is bidirectional.

\subsubsection{Control Bus}

Control bus is a term which referes to any control lines (such as read and write
lines or clock lines)  which are neither address nor data bus. The control bus
in our case is 5 bits wide and consists of:

\begin{table}[H]
	\centering
	\begin{tabular}{| c | r |}
		\hline
		\textbf{Signal} & \textbf{Description}\\
		\hline
		\hline
		$MR$ & Master Reset \\
		\hline
		$\lnot WR$  & Write Not\\
		\hline
		$\lnot RD$  & Read Not \\
		\hline
		$\lnot MS1$ & Module Select 1 Not \\
		\hline
		$\lnot MS2$ & Module Select2 Not\\
		\hline
	\end{tabular}
	\caption{Signals on the control bus}
	\label{tab:ctrl_bus}
\end{table}


\paragraph{Master Reset}

A high level on the $MR$ lane signals to the peripherials that a reset of all
registers and states should occure. This is needed for the serial console and
the DAC.

\paragraph{Write Not}
A low level on the $\lnot WR$ lane signals the corresponding modules that the 
data on
the data bus should be written to the register on the address specified from the
address bus.

\paragraph{Read Not}
A low level on the $\lnot RD$ lane signals the corresponding modules that the 
data
from the register specified by the address on the address bus should be written
to the data bus.

\paragraph{Module Select 1 and 2 Not}

A low level on one of these lines signals the corresponding module that the
data on address data and the control lines is meant for it.

\paragraph{Sepearation of $\lnot RD$/$\lnot WR$ and$\lnot MS1$/$\lnot MS2$}

The Read Not and Write Not lines could be combined into one line $\lnot RD/WR$.
The same can be done for the Module Select lanes. In both cases this would
have made wiring inside the finished modules more difficult and if both were
combined the bus would not be able to not perform an action at any given
point in time. Therefore these signals have not been combined.

\subsection{Von Neumann Archtiecture}

The term ``von Neumann architecture`` referrs to a type of computer architecture
which referres to almost any modern computer system. It describes the in this
thesis used Human input and output parts and the general workings of modern
processors with the ALU\footnote{ALU...arithmetic logic unit} or the CA
\footnote{CA...Central Arithmetic Part} as well as means to interface with its
operator\cite{neumann}.

In his thesis ``First Draft of a Report on the EDVAC`` he writes about human 
input:

\vspace{1cm}

``Once these instructions are given to the device, it must be able to carry them out completely and
without any need for further intelligent human intervention. At the end of the required operations
the device must record the results again in one of the forms referred to above.``\cite[p.7]{neumann}

\vspace{1cm}

This can be applied to the hardware implemented in this thesis, as well as
other general computing systems. The EDVAC, which his thesis referres to, was a
computer developed for military purposes. Much like the EDVAC, the CPU in this
thesis is responsible for arithemtic operations and code interpetation. The
peripherials are what is referred to as the input and output devices in his
report. Though the for examples used ATMega2650 utilizes a harvard architecture
``In order to maximize performance and parallellism``\cite[p.11]{atmega2560} the
more general descriptions of computational operations still apply to this
thesis. The differences between a harvard architecture and a von neumann 
architecture are shown in figure \ref{fig:harvard_neumann}

\begin{figure}[H]
	\includesvg[width=.5\textwidth, angle=0]{pics/harvard}
	\includesvg[width=.5\textwidth, angle=0]{pics/neumann}
	\caption{Harvard(left) vs Von-Neumann architecture(right);\\
Source: \url{https://en.wikipedia.org/}}
	\label{fig:harvard_neumann}
\end{figure}
