\subsubsection{Meilensteine}

\paragraph{Brauns}
Tabelle \ref{tab:mst_brauns} zeigt die zu Projektbeginn festgelegten Meilensteine.
\begin{table}[H]
	\centering
	\begin{tabular}{| c | r |}
		\hline
		\textbf{Datum} & \textbf{Meilenstein}\\
		\hline
		\hline
		21.10.2019 & Pflichtenheft, Grobdesign, Testplan, Core-Grundstruktur \\
		\hline
		17.12.2019 & Komplettes Core-Simulationsdesign\\
		\hline
		21.01.2020 & Simpler SoC (core+memory+LEDs) und Implementierung in FPGA \\
		\hline
		18.02.2020 & Anbindung an diskrete Peripherie\\
		\hline
		10.03.2020 & UART-Bootloader\\
		\hline
	\end{tabular}
	\caption{Meilensteine Brauns Armin}
	\label{tab:mst_brauns}
\end{table}

\paragraph{Plank}

Tabelle \ref{tab:mst_plank} zeigt die zu Projektbeginn festgelegten 
Meilensteine. Der Meilensteininhalt wurde nach der Aufgabenstellung zugeteilt,
die Meilensteintermine wurden vom Betreuer festgelegt.

\begin{table}[H]
	\centering
	\begin{tabular}{| c | r |}
		\hline
		\textbf{Datum} & \textbf{Meilenstein}\\
		\hline
		\hline
		22.10.2019 & Pflichtenheft, Grobdesign, Testplan, Beschaffung der Unterlagen\\
		\hline
		10.12.2019 & Serielle Schnitstelle\\
		\hline
		14.01.2020 & 8-Bit-Parallelport\\
		\hline
		12.02.2020 & Dokumentation\\
		\hline
		10.03.2020 & 4-Bit-DAC mit R-2R-Netz\\
		\hline
	\end{tabular}
	\caption{Meilensteine Plank Daniel}
	\label{tab:mst_plank}
\end{table}

\subsubsection{Work time reference}

\paragraph{Brauns}

Table \ref{tab:brauns_work} shows the times worked.

\begin{longtable}{| l | c | p{100mm} |}
	\hline
	\textbf{Date} & \textbf{Duration [h]} & \textbf{Task}\\
	\hline
	\hline
	2018-12-11 & 3 & Create Quartus project, implement first proof-of-concept design \\
	\hline
	2018-12-19 & 3 & ALU design and corresponding test bench \\
	\hline
	2019-01-18 & 5 & First processor prototype capable of running programs \\
	\hline
	2019-01-20 & 2 & Preliminary firmware build system \\
	\hline
	2019-01-28 & 6 & VGA generator prototype \\
	\hline
	2019-01-29 & 6 & VGA text renderer \\
	\hline
	2019-02-04 & 4 & Control and Status Registers \\
	\hline
	2019-02-07 & 12 & 16550 compatible UART \\
	\hline
	2019-02-09 & 5 & UART boot loader \\
	\hline
	2019-02-09 & 1.5 & Build system improvements \\
	\hline
	2019-02-18 & 6 & Unify simulation and synthesis SoC entities \\
	\hline
	2019-02-19 & 2 & Debug and fix text renderer timing issues \\
	\hline
	2019-02-19 & 2 & Add interrupts to UART \\
	\hline
	2019-02-19 & 1 & Handle UART interrupts in payload \\
	\hline
	2019-02-20 & 4 & Makefile-based build system \\
	\hline
	2019-02-20 & 0.5 & Documentation \\
	\hline
	2019-02-21 & 1 & Debug and fix VHDL simulation warnings \\
	\hline
	2019-02-26 & 2 & Diagnosing and fixing core bugs \\
	\hline
	2019-02-26 & 3 & Exception control unit \\
	\hline
	2019-02-26 & 2 & Illegal instruction exceptions \\
	\hline
	2019-03-01 & 0.5 & Breakpoint + environment call exceptions \\
	\hline
	2019-03-01 & 1 & Build system improvements \\
	\hline
	2019-03-04 & 1 & Misc bug fixes \\
	\hline
	2019-03-10 & 2 & Diagnose and fix interrupt related processor bug \\
	\hline
	2019-03-11 & 3 & CSR illegal instruction exceptions \\
	\hline
	2019-03-12 & 1 & Preparations for pipelining core \\
	\hline
	2019-03-21 & 0.5 & Switch to bare-metal compiler toolchain \\
	\hline
	2019-04-03 & 0.5 & Build system improvements \\
	\hline
	2019-04-04 & 5 & Design changes to improve timing \\
	\hline
	2019-04-05 & 4 & Port design to Arty A7 and Vivado \\
	\hline
	2019-04-06 & 3 & Port design to Arty A7 and Vivado \\
	\hline
	2019-04-06 & 3 & TMDS generator frontend \\
	\hline
	2019-04-07 & 1 & Add DVI output to Arty SoC \\
	\hline
	2019-04-11 & 0.5 & Simulation tooling \\
	\hline
	2019-04-19 & 1 & Split into core and soc respositories \\
	\hline
	2019-04-19 & 3 & Cleanup after repo split \\
	\hline
	2019-04-21 & 4 & Text renderer work \\
	\hline
	2019-04-22 & 4 & Vivado project generator script \\
	\hline
	2019-04-22 & 1 & Target Arty S7 \\
	\hline
	2019-04-25 & 3 & Colors in text renderer \\
	\hline
	2019-05-07 & 3 & Firmware tooling \\
	\hline
	2019-05-07 & 3 & UART resiliency \\
	\hline
	2019-05-08 & 4 & Software ring buffer \\
	\hline
	2019-06-05 & 4 & WS2812 driver \\
	\hline
	2019-07-04 & 2 & Vivado DDR3 IP \\
	\hline
	2019-07-10 & 3 & DDR3 interface \\
	\hline
	2019-07-13 & 6 & memory development \\
	\hline
	2019-07-14 & 6 & memory debugging \\
	\hline
	2019-07-19 & 3 & Vivado in-circuit debugging \\
	\hline
	2019-07-25 & 5 & Test HDMI output in hardware \\
	\hline
	2019-07-26 & 5 & Add parity to UART \\
	\hline
	2019-09-19 & 1 & Remove DE0/Quartus support \\
	\hline
	2019-10-04 & 1 & UART Modem \\
	\hline
	2019-10-04 & 3 & VHDL-2008 memory simulation model \\
	\hline
	2019-10-10 & 2 & new core \\
	\hline
	2019-10-13 & 5 & new core \\
	\hline
	2019-10-14 & 1 & new core \\
	\hline
	2019-10-19 & 6 & new core \\
	\hline
	2019-10-22 & 2 & Merge new core \\
	\hline
	2019-10-31 & 5 & Unify simulation and vivado SoC entities \\
	\hline
	2019-11-14 & 1 & Fix \texttt{to\_integer} simulation warnings \\
	\hline
	2019-11-21 & 5 & DDR3 simulation entity \\
	\hline
	2019-12-01 & 3 & Investigate Free toolchains \\
	\hline
	2019-01-02 & 0.5 & Code cleanup \\
	\hline
	2019-01-12 & 4 & Work toward free toolchain \\
	\hline
	2019-01-18 & 5 & Toolchain testing and debugging \\
	\hline
	2019-01-23 & 1 & UART improvements \\
	\hline
	2019-01-24 & 6 & Switch whole project to Free toolchain \\
	\hline
	2019-01-25 & 3 & Memory self-test routines \\
	\hline
	2019-01-25 & 0.5 & Prepare ALU for mul/div \\
	\hline
	2019-02-01 & 7 & Simplify core \\
	\hline
	2019-02-02 & 5 & Compliance tests and core bug fixing \\
	\hline
	2019-02-02 & 2 & GitLab CI \\
	\hline
	2019-02-04 & 1 & Update toolchain \\
	\hline
	2019-02-08 & 5 & Investigate LiteEth ethernet core \\
	\hline
	2019-02-09 & 5 & Develop missing LiteEth features \\
	\hline
	2019-02-11 & 4 & Add LiteEth to SoC \\
	\hline
	2019-02-16 & 2 & LiteEth debugging firmware routines \\
	\hline
	2019-02-18 & 4 & LiteEth simulation model \\
	\hline
	2019-03-01 & 2 & Dependency updates \\
	\hline
	2019-03-02 & 2 & Merge synthesis and simulation socs \\
	\hline
	2019-03-06 & 2 & External bus interface \\
	\hline
	2019-03-06 & 3 & Test external bus \\
	\hline
	2019-03-09 & 3 & Debug UART boot \\
	\hline
	2019-03-15 & 1 & Remove Vivado support \\
	\hline
	2019-03-28 & 4 & Documentation \\
	\hline
	2019-03-28 & 1 & Refactor ALU \\
	\hline
	2019-03-29 & 2 & Documentation \\
	\hline
	2019-03-29 & 3 & Add formal verification \\
	\hline
	2019-03-30 & 3 & Documentation \\
	\hline
	2019-03-31 & 4 & Documentation \\
	\hline
	\hline
	2020-04-01 & \textbf{SUM} & 277h\\
	\hline
\caption{Work time reference - Brauns}
\label{tab:brauns_work}
\end{longtable}
\newpage
\paragraph{Plank}

Table \ref{tab:plank_work} shows the times worked.

\begin{longtable}{| l | c | p{100mm} |}
	\hline
	\textbf{Date} & \textbf{Duration [h]} & \textbf{Task}\\
	\hline
	\hline
	2019-09-06	& 4.25	& start of thesis document \\
	\hline
	2019-09-07	& 2.25	& planning of thesis \\
	\hline
	2019-09-20	& 1	& planning part two, input into database \\
	\hline
	2019-09-23	& 0.5	& corrections in database \\
	\hline
	2019-09-25	& 0.5	& discussions with supervisor about deadlines\\
	\hline
	2019-09-27	& 0.25	& reformatting and discussion about database entry\\
	\hline
	2019-10-11	& 2	& tests and high level design for MS1\\
	\hline
	2019-10-12	& 3.75	& gather PDFs for MS1\\
	\hline
	2019-10-16	& 2.5	& tests and high level design for MS1\\
	\hline
	2019-10-17	& 2.5	& tests and high level design for MS1\\
	\hline
	2019-10-20	& 4.25	& tests and high level design for MS1\\
	\hline
	2019-10-22	& 3.5	& Finalisation tests and high level design for MS1\\
	\hline
	2019-12-08	& 4.75	& Download thesis template and implement\\
	\hline
	2020-01-03	& 6.75	& Planning and early schematics of serial module\\
	\hline
	2020-01-04	& 2	& Parallel port layout\\
	\hline
	2020-01-08	& 3.75	& Serial console breadboard test\\
	\hline
	2020-01-11	& 2.5	& Attempting interaction with 16550\\
	\hline
	2020-01-18	& 4.5	& Attempting interaction with 16550 nailing down errors\\
	\hline
	2020-01-18	& 3	& Attempting interaction with 16550\\
	\hline
	2020-02-25	& 1	& Help partner with hosting tar.gz file\\
	\hline
	2020-01-26	& 6.25	& Attempting interaction with 16550 no output\\
	\hline
	2020-02-01	& 3	& Attempting interaction with 16550 quartz doesn't oscillate\\
	\hline
	2020-02-07	& 5.5	& Attempting to make 1.8432MHz oscillators oscillate\\
	\hline
	2020-02-08	& 3	& Oscillation succeeded\dots{} finaly\\
	\hline
	2020-02-09	& 7.75	& Transmit character in serial via 16550\\
	\hline
	2020-02-10	& 4	& Serial console eurocard\\
	\hline
	2020-02-11	& 5	& Serial console and arduino eurocard\\
	\hline
	2020-02-12	& 5	& Serial console and arduino eurocard\\
	\hline
	2020-02-13	& 4	& Serial console and arduino eurocard testing\\
	\hline
	2020-02-14	& 6	& Serial console and arduino eurocard code\\
	\hline
	2020-02-15	& 3.5	& Serial console and arduino eurocard code\\
	\hline
	2020-02-18	& 3.5	& ECHO! Program\\
	\hline
	2020-02-19	& 3.5	& DAC schematic and breadboard beginning\\
	\hline
	2020-02-20	& 2.25	& DAC driver simulation attempt\\
	\hline
	2020-03-01	& 3.25	& Level shifter test and verification\\
	\hline
	2020-03-04	& 2	& DAC fifo breadboard\\
	\hline
	2020-03-08	& 7.5	& breadboard final test DAC and FIFO and eurocard\\
	\hline
	2020-03-10	& 4.75	& DAC module test and sine generation code\\
	\hline
	2020-03-11	& 4.25	& textadventure start\\
	\hline
	2020-03-12	& 4.25	& textadventure polling dac and 16550\\
	\hline
	2020-03-13	& 4.5	& finalisation of everything in school COVID-19\\
	\hline
	2020-03-14	& 5	& textadventure DAC mode implementation\\
	\hline
	2020-03-15	& 4	& textadventure sound routines\\
	\hline
	2020-03-17	& 4	& textadventure gameplay\\
	\hline
	2020-03-18	& 6	& documentation\\
	\hline
	2020-03-19	& 4	& documentation\\
	\hline
	2020-03-20	& 3	& documentation\\
	\hline
	2020-03-21	& 1	& textadventure gamplay\\
	\hline
	2020-03-22	& 0.5	& textadventure gamplay\\
	\hline
	2020-03-23	& 6.25	& documentation\\
	\hline
	2020-03-24	& 6.75	& documentation\\
	\hline
	2020-03-25	& 7.25	& documentation\\
	\hline
	2020-03-26	& 7	& documentation\\
	\hline
	2020-03-27	& 5.75	& documentation\\
	\hline
	2020-03-28	& 4.5	& documentation\\
	\hline
	2020-03-29	& 6.5	& documentation\\
	\hline
	2020-03-30	& 9.75	& documentation\\
	\hline
	2020-03-31	& 0	& documentation\\
	\hline
	\hline
	2020-04-01      & \textbf{SUM} & 229.5h\\
	\hline
\caption{Work time reference - Plank}
\label{tab:plank_work}
\end{longtable}