library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
	port (
		clk       : in std_logic;
		reset     : in std_logic;
		enable    : in std_logic;
		direction : in std_logic;

		count_out : out std_logic_vector(7 downto 0)
	);
end counter;

architecture behaviour of counter is
	signal count : unsigned(7 downto 0) := (others => '0');
begin
	proc: process(clk)
	begin
		if reset then
			count <= (others => '0');
		elsif rising_edge(clk) and enable = '1' then
			if direction = '1' then
				count <= count + 1;
			else
				count <= count - 1;
			end if;
		end if;
	end process;

	count_out <= std_logic_vector(count);
end behaviour;