Add information about external bus

Diplomschrift.bib

@@ -71,3 +71,9 @@
 	title  = {GTKWave},
 	url    = {http://gtkwave.sourceforge.net},
 }
+
+@online{riscv-compliance,
+    author = {Jeremy Bennett, Lee Moore},
+    title  = {RISC-V Compliance Task Group},
+    url    = {https://github.com/riscv/riscv-compliance},
+}

preamble.tex

@@ -143,7 +143,7 @@
 \makeindex
 
 %%% BibLaTeX settings
-\usepackage[style = verbose, dashed=false, citestyle = authoryear-ibid, maxcitenames=1]{biblatex}
+\usepackage[style = verbose, dashed=false, citestyle = ieee]{biblatex}
 \usepackage{csquotes}
 %\addbibresource{./bibliographies/MR.bib}
 \DeclareNameAlias{sortname}{family-given}

sections/soc/soc.tex

@@ -143,4 +143,26 @@ The exact timing differs between models, so all periods can be customized using
 
 % TODO
 
+\subsection{External Bus}
+
+Bridging the internal SoC bus with the external peripheral bus requires a few steps. For one, the external data bus is bidirectional, so tri-state outputs must be used on the FPGA. In addition, the internal bus arbitrates components using addresses alone, while the external bus uses chip enable signals and overlapping address spaces.
+
+Due to a mistake in the adapter board layout, the nibbles of the address and data buses are reversed (MSB to LSB are pins 7 to 0 on the FPGA, but 3 to 0 followed by 7 to 4 on the board). Thanks to the completely arbitrary mapping of FPGA pins, this can be mitigated without using any additional resources.
+
+\section{Testing}
+
+\subsection{RISC-V Compliance Tests}
+
+The RISC-V Compliance Test Suite\cite{riscv-compliance} can be used to empirically confirm the correct functionality of a RISC-V processor. It consists of a series of programs that perform some operations related to a specific feature, then write some result data to a memory region. This memory region is then compared to a ``golden signature'', which was produced by a processor implementation that is known to be correct.
+
+The initial implementation of the compliance tests uncovered several bugs in the processor core:
+
+\begin{itemize}
+ \item The bitshift instructions (SLL, SRL, SRA, etc.) must, according to the RISC-V standard, only use the lower 5 bits of the second operand as a shift offset. The implementation used all 31 bits instead, causing a test failure.
+ \item Reading a signed value of a size less than 32 bits from memory would not perform proper sign extension. For example, reading a byte value of 0xFF (-1) would result in an expanded machine word of 0x0000_00FF (255) instead of 0xFFFF_FFFF.
+ \item The \icode{SLTIU} (Set less than immediate; unsigned) instruction compares a given register with a constant provided as part of the instruction (the immediate). While the comparison is unsigned, the 12-bit immediate must be sign-extended as if it were a signed integer. The implementation wrongly assumed that the sign-extension should be unsigned as well.
+ \item The Instruction Set Manual specifies exceptions that must be raised when a misaligned memory access occurs. These exceptions were not yet implemented, but since the compliance tests check for them, the functionality was added to make the tests pass.
+\end{itemize}
+
+Since these tests are easily automated, they were added to the GitLab Continuous Integration (CI) configuration. Whenever a new git commit is pushed to GitLab, the tests are run automatically, and any failures are reported to the responsible committer via email.
 \end{document}

sections/vhdl_intro/vhdl_intro.tex

@@ -14,7 +14,7 @@ Other than a text editor, the following Free Software packages have to be instal
  \item[\icode{ghdl}\cite{ghdl}] to analyze, compile, and simulate the design
  \item[\icode{gtkwave}\cite{gtkwave}] to view the simulation waveform files
  \item[\icode{yosys}\cite{yosys}] to synthesize the design
- \item[\icode{ghdlsynth-beta}\cite{yosys}] to synthesize the design
+ \item[\icode{ghdlsynth-beta}\cite{ghdlsynth-beta}] to synthesize the design
  \item[\icode{nextpnr-xilinx}\cite{nextpnr-xilinx}] to place and route the design 
  \item[\icode{Project X-Ray}\cite{prjxray}] for FPGA layout data and bitstream tools
  \item[\icode{openFPGALoader}\cite{open-fpga-loader}] to load the bitstream onto the FPGA