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ee6978f189
12 changed files with 16 additions and 751 deletions
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@ -29,17 +29,6 @@
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volume = {1997}
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volume = {1997}
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}
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}
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@techreport{neumann,
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type = {Report},
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key = {W–670–ORD–4926},
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month = Jun,
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year = {1945},
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title = {First Draft of a Report on the EDVAC},
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institution = {United States Army Ordnance Department and the University of Pennsylvania},
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volume = {1945},
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url = {http://abelgo.cn/cs101/papers/Neumann.pdf}
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}
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@Manual{max232,
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@Manual{max232,
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month = Feb,
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month = Feb,
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year = {1989},
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year = {1989},
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main.pdf
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main.pdf
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pics/harvard.svg
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pics/harvard.svg
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|
||||||
</g>
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|
||||||
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|
||||||
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|
||||||
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|
|
||||||
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|
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|
||||||
</g>
|
|
||||||
</svg>
|
|
||||||
|
Before Width: | Height: | Size: 17 KiB |
|
|
@ -412,13 +412,8 @@ minimum height=1cm, align=center, text width=3cm, draw=black, fill=blue!30]
|
||||||
|
|
||||||
\newcommand\instrset{rv32i}
|
\newcommand\instrset{rv32i}
|
||||||
|
|
||||||
\newcommand{\entityheader}[1]{
|
\newcommand{\entityheader}[2]{
|
||||||
\lstinputlisting[
|
\lstinputlisting[style=vhdlstyle,title=\texttt{#2}]{#1}
|
||||||
style=vhdlstyle,
|
|
||||||
label={lst:entity-header-#1},
|
|
||||||
caption={Header for #1 entity},
|
|
||||||
title=\texttt{#1.vhd},
|
|
||||||
]{entities/#1_entity.vhd}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
\usepackage{tcolorbox}
|
\usepackage{tcolorbox}
|
||||||
|
|
|
||||||
|
|
@ -20,29 +20,6 @@ layout of the Atari Parallel Bus Interface is shown as used on the Atari 800XL.
|
||||||
\label{fig:atari_pbi}
|
\label{fig:atari_pbi}
|
||||||
\end{figure}
|
\end{figure}
|
||||||
|
|
||||||
\paragraph{System Bus}
|
|
||||||
|
|
||||||
In some architectures the backbone parallel bus consisting of data- address- and
|
|
||||||
control bus is called the system bus. The system bus even has its own wikipedia
|
|
||||||
article \footnote{\url{https://en.wikipedia.org/wiki/System_bus}} and the
|
|
||||||
picture seen in
|
|
||||||
figure \ref{fig:sysbus}, which has been taken from this wikipedia article, even
|
|
||||||
shows the exact same parts. However the origin of this term could not be
|
|
||||||
determined and its use was the most common when describing the interface between
|
|
||||||
the fabric of the CPU with external parts via this interface on a motherboard,
|
|
||||||
which ran on system clock speed and was synchronized with the processor.
|
|
||||||
The term parallel bus was chosen for this thesis because the bus runs on an
|
|
||||||
independant clock speed and only interacts with the processor asynchronous to
|
|
||||||
its clock. The term front side bus would be more fitting but not used because of
|
|
||||||
its affiliation with intel products.
|
|
||||||
|
|
||||||
\begin{figure}[H]
|
|
||||||
\includesvg[width=\textwidth, angle=0]{pics/sysbus}
|
|
||||||
\caption{System bus structural diagram; Source: \url{https://en.wikipedia.org/}}
|
|
||||||
\label{fig:sysbus}
|
|
||||||
\end{figure}
|
|
||||||
|
|
||||||
|
|
||||||
\subsubsection{Address Bus}
|
\subsubsection{Address Bus}
|
||||||
|
|
||||||
The address bus contains the nescessary data lines for addressing the individual
|
The address bus contains the nescessary data lines for addressing the individual
|
||||||
|
|
@ -96,41 +73,3 @@ to the data bus.
|
||||||
A low level on one of these lines signals the corresponding module that the
|
A low level on one of these lines signals the corresponding module that the
|
||||||
data on address data and the control lines is meant for it.
|
data on address data and the control lines is meant for it.
|
||||||
|
|
||||||
\subsection{Von Neumann Archtiecture}
|
|
||||||
|
|
||||||
The term ``von Neumann architecture`` referrs to a type of computer architecture
|
|
||||||
which referres to almost any modern computer system. It describes the in this
|
|
||||||
thesis used Human input and output parts and the general workings of modern
|
|
||||||
processors with the ALU\footnote{ALU...arithmetic logic unit} or the CA
|
|
||||||
\footnote{CA...Central Arithmetic Part} as well as means to interface with its
|
|
||||||
operator\cite{neumann}.
|
|
||||||
|
|
||||||
In his thesis ``First Draft of a Report on the EDVAC`` he writes about human
|
|
||||||
input:
|
|
||||||
|
|
||||||
\vspace{1cm}
|
|
||||||
|
|
||||||
``Once these instructions are given to the device, it must be able to carry them out completely and
|
|
||||||
without any need for further intelligent human intervention. At the end of the required operations
|
|
||||||
the device must record the results again in one of the forms referred to above.``\cite[p.7]{neumann}
|
|
||||||
|
|
||||||
\vspace{1cm}
|
|
||||||
|
|
||||||
This can be applied to the hardware implemented in this thesis, as well as
|
|
||||||
other general computing systems. The EDVAC, which his thesis referres to, was a
|
|
||||||
computer developed for military purposes. Much like the EDVAC, the CPU in this
|
|
||||||
thesis is responsible for arithemtic operations and code interpetation. The
|
|
||||||
peripherials are what is referred to as the input and output devices in his
|
|
||||||
report. Though the for examples used ATMega2650 utilizes a harvard architecture
|
|
||||||
``In order to maximize performance and parallellism``\cite[p.11]{atmega2560} the
|
|
||||||
more general descriptions of computational operations still apply to this
|
|
||||||
thesis. The differences between a harvard architecture and a von neumann
|
|
||||||
architecture are shown in figure \ref{fig:harvard_neumann}
|
|
||||||
|
|
||||||
\begin{figure}[H]
|
|
||||||
\includesvg[width=.5\textwidth, angle=0]{pics/harvard}
|
|
||||||
\includesvg[width=.5\textwidth, angle=0]{pics/neumann}
|
|
||||||
\caption{Harvard(left) vs Von-Neumann architecture(right);\\
|
|
||||||
Source: \url{https://en.wikipedia.org/}}
|
|
||||||
\label{fig:harvard_neumann}
|
|
||||||
\end{figure}
|
|
||||||
|
|
|
||||||
|
|
@ -160,21 +160,6 @@ modern CD Drives, an ASIC
|
||||||
with an internal PLL is used, thus the required quartz can no longer be sourced
|
with an internal PLL is used, thus the required quartz can no longer be sourced
|
||||||
via conventional electronic resellers.
|
via conventional electronic resellers.
|
||||||
|
|
||||||
\subsubsection{DAC Module Read}
|
|
||||||
|
|
||||||
On a read the status bits of the FIFO, which have been latched into the 74HC374
|
|
||||||
D-Flip-Flop, are written onto the Data bus. Table \ref{tab:dac_data}
|
|
||||||
|
|
||||||
\begin{table}[H]
|
|
||||||
\centering
|
|
||||||
\begin{tabular}{ c | r |}
|
|
||||||
|
|
||||||
\end{tabular}
|
|
||||||
\caption{The layout of the Data Bus on read}
|
|
||||||
\label{tab:dac_data}
|
|
||||||
\end{table}
|
|
||||||
|
|
||||||
|
|
||||||
\subsubsection{Demonstration Software}
|
\subsubsection{Demonstration Software}
|
||||||
|
|
||||||
\paragraph{SAW Generator}
|
\paragraph{SAW Generator}
|
||||||
|
|
|
||||||
|
|
@ -79,16 +79,3 @@ diodes produce the 0.7V offset and prevent the parallel bus from rising to
|
||||||
\caption{The internal clamping diodes of the Analog Discovery 2\cite{ad2}}
|
\caption{The internal clamping diodes of the Analog Discovery 2\cite{ad2}}
|
||||||
\label{fig:ad2_diode}
|
\label{fig:ad2_diode}
|
||||||
\end{figure}
|
\end{figure}
|
||||||
|
|
||||||
\subsubsection{Final Module}
|
|
||||||
|
|
||||||
The final module can be seen in figure \ref{fig:fpga_mod} without the FPGA
|
|
||||||
attached. The blue modules below are the level shifters.
|
|
||||||
|
|
||||||
\begin{figure}[H]
|
|
||||||
\centering
|
|
||||||
\includegraphics[width=\textwidth, angle=0]{pics/fpga_int}
|
|
||||||
\caption{The final FPGA interface module with the level shifters}
|
|
||||||
\label{fig:fpga_mod}
|
|
||||||
\end{figure}
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -26,13 +26,13 @@ It is constructed according to the traditional RISC pipeline:
|
||||||
|
|
||||||
\section{Control}
|
\section{Control}
|
||||||
|
|
||||||
\entityheader{control}
|
\entityheader{entities/control_entity.vhd}{control.vhd}
|
||||||
|
|
||||||
The control unit is responsible for coordinating subcomponents and the data flow between them. Internally, it is based on \icode{instruction\_info\_t} structures, which contain all the information required to pass an instruction along the different pipeline stages. Before the fetch stage, when an instruction is first scheduled, it contains only the instruction's address (because nothing else is known about it). Then, information is added incrementally by the different stages.
|
The control unit is responsible for coordinating subcomponents and the data flow between them. Internally, it is based on \icode{instruction\_info\_t} structures, which contain all the information required to pass an instruction along the different pipeline stages. Before the fetch stage, when an instruction is first scheduled, it contains only the instruction's address (because nothing else is known about it). Then, information is added incrementally by the different stages.
|
||||||
|
|
||||||
\section{Decoder}
|
\section{Decoder}
|
||||||
|
|
||||||
\entityheader{decoder}
|
\entityheader{entities/decoder_entity.vhd}{decoder.vhd}
|
||||||
|
|
||||||
The decoder receives an instruction and interprets it. Among others, it determines
|
The decoder receives an instruction and interprets it. Among others, it determines
|
||||||
|
|
||||||
|
|
@ -45,31 +45,31 @@ The decoder receives an instruction and interprets it. Among others, it determin
|
||||||
|
|
||||||
\section{Registers}
|
\section{Registers}
|
||||||
|
|
||||||
\entityheader{registers}
|
\entityheader{entities/registers_entity.vhd}{registers.vhd}
|
||||||
|
|
||||||
The registers store the 32 general-purpose values required by \instrset{} (each 32-bit wide). They are accessible through two read ports and one write port. As specified by the RISC-V standard, the first register (\icode{x0}) is hard-wired to 0, and any writes to it are ignored.
|
The registers store the 32 general-purpose values required by \instrset{} (each 32-bit wide). They are accessible through two read ports and one write port. As specified by the RISC-V standard, the first register (\icode{x0}) is hard-wired to 0, and any writes to it are ignored.
|
||||||
|
|
||||||
\section{Arithmetic and Logic Unit (ALU)}
|
\section{Arithmetic and Logic Unit (ALU)}
|
||||||
|
|
||||||
\entityheader{alu}
|
\entityheader{entities/alu_entity.vhd}{alu.vhd}
|
||||||
|
|
||||||
The ALU contains a math/logic unit as well as a comparator. It is used both explicitly by instructions such as \icode{add} or \icode{shiftl}, as well as to add offsets to base addresses for memory instructions and to decide whether an instructions should branch.
|
The ALU contains a math/logic unit as well as a comparator. It is used both explicitly by instructions such as \icode{add} or \icode{shiftl}, as well as to add offsets to base addresses for memory instructions and to decide whether an instructions should branch.
|
||||||
|
|
||||||
\section{Control and Status Registers (CSR)}
|
\section{Control and Status Registers (CSR)}
|
||||||
|
|
||||||
\entityheader{csr}
|
\entityheader{entities/csr_entity.vhd}{csr.vhd}
|
||||||
|
|
||||||
The control and status registers contain configurations relevant to the core itself. For example, they can be used to control interrupts.
|
The control and status registers contain configurations relevant to the core itself. For example, they can be used to control interrupts.
|
||||||
|
|
||||||
\section{Memory Arbiter}
|
\section{Memory Arbiter}
|
||||||
|
|
||||||
\entityheader{memory_arbiter}
|
\entityheader{entities/memory_arbiter_entity.vhd}{memory\_arbiter.vhd}
|
||||||
|
|
||||||
Since both fetch and memory stages need to access the same system memory, access to this common resource has to be controlled. The memory arbiter acts as a proxy for both fetch and data memory requests and stalls either until the other one completes.
|
Since both fetch and memory stages need to access the same system memory, access to this common resource has to be controlled. The memory arbiter acts as a proxy for both fetch and data memory requests and stalls either until the other one completes.
|
||||||
|
|
||||||
\section{Exception Control}
|
\section{Exception Control}
|
||||||
|
|
||||||
\entityheader{exception_control}
|
\entityheader{entities/exception_control_entity.vhd}{exception\_control.vhd}
|
||||||
|
|
||||||
Several components in the core may raise a synchronous exception when an unexpected error (such as a malformed instruction or an unaligned memory access) occurs. Additionally, asynchronous interrupts (like from a timer or a UART) can be triggered externally. When an exception or an enabled interrupt is registered, program flow is diverted to the trap handler, defined using the machine trap vector (\icode{mtvec}) CSR.
|
Several components in the core may raise a synchronous exception when an unexpected error (such as a malformed instruction or an unaligned memory access) occurs. Additionally, asynchronous interrupts (like from a timer or a UART) can be triggered externally. When an exception or an enabled interrupt is registered, program flow is diverted to the trap handler, defined using the machine trap vector (\icode{mtvec}) CSR.
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -25,28 +25,15 @@ Other than a text editor, the following Free Software packages have to be instal
|
||||||
|
|
||||||
A simple starting design is an up/down counter. The following VHDL code describes the device:
|
A simple starting design is an up/down counter. The following VHDL code describes the device:
|
||||||
|
|
||||||
\lstinputlisting[
|
\lstinputlisting[style=vhdlstyle,title=\texttt{counter.vhd}]{vhdl/counter.vhd}
|
||||||
style=vhdlstyle,
|
|
||||||
label={lst:counter},
|
|
||||||
caption={Counter entity},
|
|
||||||
title=\texttt{counter.vhd},
|
|
||||||
]{vhdl/counter.vhd}
|
|
||||||
|
|
||||||
In order to test this design, a test bench has to be created:
|
In order to test this design, a test bench has to be created:
|
||||||
|
|
||||||
\lstinputlisting[
|
\lstinputlisting[style=vhdlstyle,title=\texttt{counter_tb.vhd}]{vhdl/counter_tb.vhd}
|
||||||
style=vhdlstyle,
|
|
||||||
label={lst:counter-tb},
|
|
||||||
caption={Counter test bench entity},
|
|
||||||
title=\texttt{counter_tb.vhd},
|
|
||||||
]{vhdl/counter_tb.vhd}
|
|
||||||
|
|
||||||
\section{Simulating a design}
|
\section{Simulating a design}
|
||||||
|
|
||||||
\begin{lstlisting}[
|
\begin{lstlisting}[style=terminal]
|
||||||
style=terminal,
|
|
||||||
label={lst:counter-sim-commands},
|
|
||||||
caption={Commands required to simulate the counter design}]
|
|
||||||
# analyze the design files
|
# analyze the design files
|
||||||
ghdl -a --std=08 *.vhd
|
ghdl -a --std=08 *.vhd
|
||||||
# elaborate the test bench entity
|
# elaborate the test bench entity
|
||||||
|
|
@ -66,16 +53,9 @@ gtkwave counter_tb.ghw counter_tb.gtkw
|
||||||
|
|
||||||
An additional Xilinx Design Constraints (XDC) file is required to assign the signals to pins on the FPGA:
|
An additional Xilinx Design Constraints (XDC) file is required to assign the signals to pins on the FPGA:
|
||||||
|
|
||||||
\lstinputlisting[
|
\lstinputlisting[title=\texttt{counter.xdc}]{vhdl/counter.xdc}
|
||||||
label={lst:counter-constraints},
|
|
||||||
caption={Counter design constraints file},
|
|
||||||
title=\texttt{counter.xdc},
|
|
||||||
]{vhdl/counter.xdc}
|
|
||||||
|
|
||||||
\begin{lstlisting}[
|
\begin{lstlisting}[style=terminal]
|
||||||
style=terminal,
|
|
||||||
label={lst:counter-synth-commands},
|
|
||||||
caption={Commands required to synthesize the counter design}]
|
|
||||||
# synthesize with yosys
|
# synthesize with yosys
|
||||||
yosys -m ghdl.so -p '
|
yosys -m ghdl.so -p '
|
||||||
ghdl --std=08 counter.vhd -e counter;
|
ghdl --std=08 counter.vhd -e counter;
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue