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base: tyrolyean:9fadf57f825877f4a2b467a70363d31e384a14f3
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tyrolyean:master
tyrolyean:merge-all
tyrolyean:batman
tyrolyean:waschtl
tyrolyean:batman-release-20200327
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compare: tyrolyean:e0cdacd1daa29c36eae093d842156bde84767c00
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tyrolyean:merge-all
tyrolyean:batman
tyrolyean:waschtl
tyrolyean:batman-release-20200327
tyrolyean:master

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5
main.tex
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@ -186,10 +186,13 @@ geschlechtsunabh"angig verstanden werden soll.
\section{Projektmanagement}
\subsection{Schlussfolgerung / Projekterfahrung}
\input{sections/Anhang/schlussfolgerung.tex}
\subsection{Projektplanung}
\DP\input{sections/Anhang/planung.tex}
\subsection{Projektterminplanung}
\allAuth\input{sections/Anhang/Projektterminplanung/projektterminplanung.tex}
\allAuth\input{sections/Anhang/flash.tex}
%\subsection{Arbeitsnachweis Diplomarbeit}
%\MR\input{sections/Anhang/Arbeitsnachweis/arbeitsnachweisMR.tex}
\AB\subfile{sections/vhdl_intro/vhdl_intro.tex}
\end{appendices}

16
planung/DP/aufgabenstellung.tex
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@ -5,14 +5,16 @@ about the internal workings of a computer system and the lack of material to
demonstrate these, hardware should be developed for educational purposes.
This hardware should not be too complex to understand but still demonstrate basic
tasks of a computer system. The targeted computing tasks are human interface
device controllers, for which
schematics and a working implementation in the hardware building
style of the Hackerspace should be built. All nescessary hardware will be
provided by the Hackerspace. If possible, already present hardware should be
used, or, if impossible, new one will be ordered. All schematics should, where
device controllers, under which a \textbf{D}igital to \textbf{A}nalog
\textbf{C}onverter\footnote{From now on reffered to simply as DAC} and a serial
console with TIA-/EIA-232 compliant voltage levels were chosen. For these
peripherials schematics and a working implementation in the hardware building
style of the hackerspace should be built. All nescessary hardware will be
provided by the Hackerspace. If possible already present hardware should be
used, if impossible new one will be ordered. All schematics should, where
possible, be constructed in Free software such as Kicad or GNU-EDA.
If possible, software-examples should be written as well, though the complexity
of these is coupled to the time left to spend on the project. Software should
If possible software-examples should be written as well, though the complexity
of these are coupled to the time left to spend on the project. Software should
be written in C, the coding convention is left to the implementer.

61
sections/Anhang/Projektterminplanung/projektterminplanung.tex
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@ -189,69 +189,68 @@ Table \ref{tab:brauns_work} shows the times worked.
\hline
2019-12-01 & 3 & Investigate Free toolchains \\
\hline
2020-01-02 & 0.5 & Code cleanup \\
2019-01-02 & 0.5 & Code cleanup \\
\hline
2020-01-12 & 4 & Work toward free toolchain \\
2019-01-12 & 4 & Work toward free toolchain \\
\hline
2020-01-18 & 5 & Toolchain testing and debugging \\
2019-01-18 & 5 & Toolchain testing and debugging \\
\hline
2020-01-23 & 1 & UART improvements \\
2019-01-23 & 1 & UART improvements \\
\hline
2020-01-24 & 6 & Switch whole project to Free toolchain \\
2019-01-24 & 6 & Switch whole project to Free toolchain \\
\hline
2020-01-25 & 3 & Memory self-test routines \\
2019-01-25 & 3 & Memory self-test routines \\
\hline
2020-01-25 & 0.5 & Prepare ALU for mul/div \\
2019-01-25 & 0.5 & Prepare ALU for mul/div \\
\hline
2020-02-01 & 7 & Simplify core \\
2019-02-01 & 7 & Simplify core \\
\hline
2020-02-02 & 5 & Compliance tests and core bug fixing \\
2019-02-02 & 5 & Compliance tests and core bug fixing \\
\hline
2020-02-02 & 2 & GitLab CI \\
2019-02-02 & 2 & GitLab CI \\
\hline
2020-02-04 & 1 & Update toolchain \\
2019-02-04 & 1 & Update toolchain \\
\hline
2020-02-08 & 5 & Investigate LiteEth ethernet core \\
2019-02-08 & 5 & Investigate LiteEth ethernet core \\
\hline
2020-02-09 & 5 & Develop missing LiteEth features \\
2019-02-09 & 5 & Develop missing LiteEth features \\
\hline
2020-02-11 & 4 & Add LiteEth to SoC \\
2019-02-11 & 4 & Add LiteEth to SoC \\
\hline
2020-02-16 & 2 & LiteEth debugging firmware routines \\
2019-02-16 & 2 & LiteEth debugging firmware routines \\
\hline
2020-02-18 & 4 & LiteEth simulation model \\
2019-02-18 & 4 & LiteEth simulation model \\
\hline
2020-03-01 & 2 & Dependency updates \\
2019-03-01 & 2 & Dependency updates \\
\hline
2020-03-02 & 2 & Merge synthesis and simulation socs \\
2019-03-02 & 2 & Merge synthesis and simulation socs \\
\hline
2020-03-06 & 2 & External bus interface \\
2019-03-06 & 2 & External bus interface \\
\hline
2020-03-06 & 3 & Test external bus \\
2019-03-06 & 3 & Test external bus \\
\hline
2020-03-09 & 3 & Debug UART boot \\
2019-03-09 & 3 & Debug UART boot \\
\hline
2020-03-15 & 1 & Remove Vivado support \\
2019-03-15 & 1 & Remove Vivado support \\
\hline
2020-03-28 & 4 & Documentation \\
2019-03-28 & 4 & Documentation \\
\hline
2020-03-28 & 1 & Refactor ALU \\
2019-03-28 & 1 & Refactor ALU \\
\hline
2020-03-29 & 2 & Documentation \\
2019-03-29 & 2 & Documentation \\
\hline
2020-03-29 & 3 & Add formal verification \\
2019-03-29 & 3 & Add formal verification \\
\hline
2020-03-30 & 3 & Documentation \\
2019-03-30 & 3 & Documentation \\
\hline
2020-03-31 & 4 & Documentation \\
2019-03-31 & 4 & Documentation \\
\hline
\hline
2020-04-01 & \textbf{SUM during school year} & 150h\\
\hline
2020-04-01 & \textbf{SUM} & 277h\\
\caption{Work time reference - Brauns}
\label{tab:brauns_work}
\end{longtable}
\newpage
\paragraph{Plank}
Table \ref{tab:plank_work} shows the times worked.

57
sections/Anhang/flash.tex
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@ -1,57 +0,0 @@
\section{Contents of the flash drive}
This section outlines the contents of the flash drive, which are two folders
``AB`` and ``DP``, one containg the files of Armin Brauns and one for Daniel
Plank respectively.
\subsection{Armin Brauns}
\begin{itemize}
\item \texttt{external/}: External dependencies as submodules
\item \texttt{firmware/}: See \texttt{firmare/README.md}
\item \texttt{sim/}: GHDL wave options and GTKWave save files for test bench
traces
\item \texttt{tests/}: High-level tests
\begin{itemize}
\item \texttt{formal/}: SymbiYosys formal verification tests
\item \texttt{riscv-compliance-target/}: YARM target for RISC-V compliance
test suite
\end{itemize}
\item \texttt{vhdl/}: All VHDL code
\begin{itemize}
\item \texttt{components/}: Various SoC components
\item \texttt{core/}: The YARM processor core
\item \texttt{memories/}: Various memory primitives, tweaked to work with
yosys
\item \texttt{simulation/}: Simulation models for primitives and external
IP
\item \texttt{tests/}: Test benches
\end{itemize}
\end{itemize}
\subsection{Daniel Plank}
\begin{table}[H]
\centering
\begin{tabular}{| c | r |}
\hline
\textbf{Directory} & \textbf{Contents}\\
\hline
\hline
code & Code sampkes written for this thesis\\
\hline
dipl & The source code for this thesis in \LaTeX\\
\hline
documents & Datasheets and documents referenced in this thesis\\
\hline
MS1 & The original milestone test plans, high level design and documents for MS1\\
\hline
schematics & Schematics for KiCAD used in this thesis\\
\hline
textadv & The textadventure written for the hardware peripherials\\
\hline
\end{tabular}
\caption{Contents of the DP directory on the flash drive}
\label{tab:flash_DP}
\end{table}

12
sections/Anhang/schlussfolgerung.tex
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@ -1,8 +1,8 @@
Aus der Projektimplementierung konnten viele Lehren gezogen werden. Messungen,
welche mittels des Analog Discoverys durchgeführt wurden, sind bis zu ungefähr
1MHz Frequenz gut zu gebrauchen, werden danach jedoch sehr stark fehlerhaft. Alle
Aus der Projektimplementierung konnten viele Lehren gezogen werden. Messungen
welche mittels des Analog Discovery durchgeführt wurden sind bis zu ungefähr
1MHz Frequenz gut zu gebrauchen werden danach jedoch sehr stark fehlerhaft. Alle
Bauteile in THT Bauform zu verwenden vereinfachte Messungen am Steckbrett
erheblich, jedoch werden diese bei hohen Frequenzen unzuverlässig. Viele
Implementationsdetails wurden durch mündlich übergebene Hinweise verbessert,
was zeigt, wie wichtig zwischenmenschliche Kommunikation in technischen
Bereichen ist.
Implementationsdetails wurden durch mündlich übergebene Hinweise verbessert
was zeigt wie wichtig zwischenmenschliche Kommunikation in technischen Bereichen
ist.

33
sections/DP/plan.tex
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@ -4,22 +4,21 @@ Planning of the peripherals was done based on the information provided on large
parts by David Oberhollenzer. A lot of his advice contributed heavily to the
direction the development went.
\subsubsection{Peripheral selection}
\subsubsection{Peripherial selection}
The selection of the hardware peripherals was done based on implementation
difficulty, common use in computer systems, relevance in current times and
whether they were fitting for demonstrative purposes.
wether they were fitting for demonstrative purposes.
\paragraph{Serial Communication interface}
\paragraph{Serial communication interface}
Serial communication interfaces have been around for a long time. They have been
used for many different applications from early mouse pointer devices
\cite{232mouse} to user input terminals\cite{vt100}
which are far away from the real computer system. They are still very common in
smaller embedded systems and in the server space, where they are used as a
simple
smaller embedded sytems and in the server space where they are used as a simple
and less error prone way to interface with the operating system and programs
running there. They are fairly easy to implement as there are interface
running there. They are fairly easy to implement as there are a interface
ICs which provide a more generic interface for serial communications
\cite{pc16550}. Most SOCs
\footnote{SOC... System on a Chip} have some form of serial communication
@ -34,24 +33,24 @@ parallel-ports for expansions and the ISA-Bus
\footnote{ISA...Industry Standard Architecture} was for some time the main way
of expansion for PCs
\footnote{PC in this thesis referrs to Computer Systems using the x86
Architecture}. Most younger people remember parallel ports as the port for
printers on their home PCs. A parallel port is easy to implement because it has
simmilar use of control, data and address lines as a processor uses internally
anyway\cite{laval_parallel}. Usage of the standard IEEE 1284 port limits the
Architecture}. Most younger people remeber parallel ports as the port for
printers on their home PCs. A prallel port is easy to implement because it has
simmilar use of control, data and address lines like a processor uses internally
anyways\cite{laval_parallel}. Usage of the standard IEEE 1284 port limits the
design to the signals on this port or makes the use of the signals on this port
obligatory.
\paragraph{Digital to Analog Converter}
Digital to Analog Converters (or more commonly DACs) are used on all modern PCs
Digital to Analog Converters or more commonly DACs are used on all modern PCs
for sound output. They have been around for longer and some external sound card
interfaces have been standardisedlike AC '97\cite{ac97}. Implementation of a
standard audio interface requires higher speed connections or more precise
timing for ac97 for example. Earlier computer systems did not have a sound card
as it doesn't have important usage for computing and user input tasks and later
as it doesn't have import usage for computing and user input tasks and later
on computer systems only had a PC speaker for diagnostics such as the IBM PC AT
\cite{ibmpc} which can only procude one specific frequency and does not have a
DAC. A DAC is not easy to implement as it requires a constant sampling rate and
DAC. A dac is not easy to implement as it requires a constant sampling rate and
a buffer to be of any practical use.
\paragraph{Graphical output / GPU}
@ -62,10 +61,10 @@ either a heavy load on the processor or dedicated hardware and due to the mostly
scientific use it was easier to just print the caracters as letters via a
printer. Drawing characters
onto a screen is by itself not an easy task as it requires, for example for
VGA, a Digital to Analog Converter with 25MHz sampling rate and a buffer to
VGA a Digital to Analog Converter with 25MHz sampling rate and a buffer to
contain all needed data for one frame or at least parts of it, while the CPU
renders the frame\cite{vga}. Screen output is one of the, if not the most,
common form of output on a computer today.
renders the frame\cite{vga}. Screen output is one of the if not the most common
form of output on a computer today.
\paragraph{Inter Integrated Circuit}
@ -81,7 +80,7 @@ understanding of IIC as it is only known in technical fields.
\paragraph{Utility analysis}
Among the above mentioned processor peripherals from the criteria mentioned
before a utility analysis was performed. To do this, different points have been
before a utility analysis was performed. To do this different point have been
credited for the criteria mentioned which can be seen in Table
\ref{tab:utility_base}. The multipliers in Table \ref{tab:utility_base} have
been applied to the points and the sums in Table \ref{tab:utility_result}

2
sections/DP/textadv/main.tex
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@ -81,7 +81,7 @@ in figure \ref{fig:textadv_pexfl}.
\begin{figure}[H]
\centering
\includesvg[height=.95\textheight]{charts/flowchart_textadv.svg}
\input{charts/flowchart_textadv.tex}
\caption{A Flow-Chart of the program execution path}
\label{fig:textadv_pexfl}
\end{figure}

5
sections/abstract.tex
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@ -1,9 +1,10 @@
\begin{otherlanguage}{ngerman}
Diese Diplomarbeit beschäftigt sich mit der Arbeitsweise von Prozessoren
und Prozessorperipherie in moderner und traditioneller Form. Sie versucht den
und Prozessorperipherie in moderner und traditioneller Form. Sie versucht
anschaulich den
Aufbau eines Computersystems in Hard- und Software zu veranschaulichen
sowie diesen zu erklären. Dafür wurde auf einem Xilinx-FPGA ein RISC-V32I
sowie diesen zu erklären. Dafür wurde auf einem XILINX FPGA ein RISC-V32I
Prozessor in VHDL
implementiert, sowie diverse Parallelbus-gebundene Hardwareperipherie entwickelt
und gebaut. Als Harwareperipherie wurde ein 8-Bit 2-Kanal DAC und eine serielle

4
sections/core/core.tex
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@ -1,4 +1,4 @@
\documentclass[../../main.tex]{subfiles}
\documentclass[../../Diplomschrift.tex]{subfiles}
\begin{document}
@ -12,7 +12,7 @@ The core implements the \instrset{} architecture as specified by the RISC-V stan
\label{fig:core-diagram}
\end{figure}
As can be seen in \autoref{fig:core-diagram}, it is constructed according to the traditional stages of a RISC pipeline:
As can be seen in \ref{fig:core-diagram}, it is constructed according to the traditional stages of a RISC pipeline:
\begin{description}
\item[Fetch] fetches the next instruction from memory.

4
sections/fpga-development.tex
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@ -1,4 +1,4 @@
\documentclass[../../main.tex]{subfiles}
\documentclass[../../Diplomschrift.tex]{subfiles}
\begin{document}
\section{FPGA Development}
@ -60,7 +60,7 @@ To refresh the reader's memory on the VHDL language, and as a quick guide for th
\subsubsection{Vendor Tools}
The conventional way to work with FPGA designs is to use the FPGA vendor's development environment for simulation, synthesis and place-and-route. All of these tools are proprietary software specialized to a certain FPGA manufacturer, so a change of hardware also requires changing to a completely different software solution.
The conventional way to work with FPGA designs is to use the FPGA vendor's development solution for simulation, synthesis and place-and-route. All of these tools are proprietary software specialized to a certain FPGA manufacturer, so a change of hardware also requires changing to a completely different software solution.
Vendor tools are usually free-of-charge for basic usage, but this also means there is no guaranteed support. During the development of this project, several bugs and missing features were found in vendor tools that required workarounds.

13
sections/intro.tex
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@ -1,8 +1,8 @@
In early 2018, more than a year before the official start of the project, after
searching for a subject for the diploma thesis, the idea of building a computer
from scratch had come up. Multiple suggestions on how to implement it were
gathered. Originally, the goal was to
design a computer consisting of seperate plug-in cards, one instruction
from scratch had come up. Multiple suggestions on how to implement it and the
scope of the project were gathered. Originally, the goal was to
design a computer consisting of seperate plug-in cards, one instruction would
residing on each. This would open up the ``black box`` of modern processor
design, showing the basic components at a macroscopic scale.
@ -10,8 +10,8 @@ The project's aim was later
redirected due to concerns about difficulty, and an FPGA-based design was opted
for instead. After
several months of implementation time, the project was split into two parts: the
peripherals and the processor core. During the development process, and to get
back to the original goal of making a processor more understandable, the
peripherals and the core processor. During the development process, and to get
back to the original goal of making a processor understandable, the
peripherals changed from being implemented in VHDL back to hardware.
This increased the required effort, but would result in a far more
understandable final product.
@ -25,8 +25,7 @@ software instead.
\label{sec:free-software}
For most of today's processors, documentation only exists on the execution of
programs (the runtime environment), not for their internals. In order to have
the biggest
programs (the runtime), not for their internals. In order the have the biggest
possible educational potential, this project is entirely "Free as in speech":
All involved software and hardware designs, as well as all the tools and
utilities required to create them, comply with the Free Software Foundation's

2
sections/result.tex
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@ -1,4 +1,4 @@
The project has been fully implemented with all functionality originally targeted.
The project is fully implemented with all functionality originally targeted.
The system has been tested and verified. All example code has been
documented and tested. Hardware implementations were created using
Free software\footnote{See \autoref{sec:free-software}} programs, while the