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1543c616db
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1543c616db |
12 changed files with 1 additions and 281 deletions
2
.gitignore
vendored
2
.gitignore
vendored
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@ -27,4 +27,4 @@
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work-*.cf
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svg-inkscape/
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core/entities/
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/sections/core/entities/
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@ -1,18 +0,0 @@
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entity alu is
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port (
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clk : in std_logic;
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enable_math : in std_logic;
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valid : out std_logic;
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operation : in alu_operation_t;
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a, b : in yarm_word;
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math_result : out yarm_word;
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-- compare inputs
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-- do signed comparisons
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enable_cmp : in std_logic;
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cmp_signed : in std_logic;
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cmp1, cmp2 : in yarm_word;
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cmp_result : out compare_result_t
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);
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end alu;
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@ -1,54 +0,0 @@
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entity control is
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generic (
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RESET_VECTOR : yarm_word
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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fetch_enable : out std_logic;
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fetch_ready : in std_logic;
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fetch_instr_out : in yarm_word;
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decoder_enable : out std_logic;
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decoder_instr_info_out : in instruction_info_t;
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registers_data_a : in yarm_word;
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registers_data_b : in yarm_word;
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alu_enable_math : out std_logic;
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alu_math_result : in yarm_word;
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alu_valid : in std_logic;
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alu_enable_cmp : out std_logic;
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alu_cmp_result : in compare_result_t;
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csr_enable : out std_logic;
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csr_ready : in std_logic;
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csr_data_read : in yarm_word;
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csr_increase_instret : out std_logic;
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datamem_enable : out std_logic;
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datamem_ready : in std_logic;
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alignment_raise_exc : out std_logic;
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alignment_exc_data : out exception_data_t;
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registers_read_enable : out std_logic;
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registers_write_enable : out std_logic;
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-- TRAP CONTROL
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may_interrupt : out std_logic;
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-- the stage that will receive an interrupt exception
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interrupted_stage : out pipeline_stage_t;
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do_trap : in std_logic;
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trap_vector : in yarm_word;
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trap_return_vec : in yarm_word;
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return_trap : out std_logic;
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-- instruction info records used as input for the respective stages
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stage_inputs : out pipeline_frames_t
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);
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end control;
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@ -1,23 +0,0 @@
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entity core is
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generic (
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HART_ID : natural;
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RESET_VECTOR : yarm_word := (others => '0')
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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-- little-endian memory interface, 4 byte address alignment
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MEM_addr : out yarm_word;
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MEM_read : out std_logic;
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MEM_write : out std_logic;
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MEM_ready : in std_logic;
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MEM_byte_enable : out std_logic_vector(3 downto 0);
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MEM_data_read : in yarm_word;
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MEM_data_write : out yarm_word;
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external_int : in std_logic;
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timer_int : in std_logic;
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software_int : in std_logic
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);
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end core;
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@ -1,36 +0,0 @@
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entity csr is
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generic (
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HART_ID : integer
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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enable : in std_logic;
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ready : out std_logic;
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instr_info_in : in instruction_info_t;
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data_write : in yarm_word;
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data_read : out yarm_word;
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increase_instret : in std_logic;
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external_int : in std_logic;
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timer_int : in std_logic;
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software_int : in std_logic;
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interrupts_pending : out yarm_word;
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interrupts_enabled : out yarm_word;
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global_int_enabled : out std_logic;
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mtvec_out : out yarm_word;
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mepc_out : out yarm_word;
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do_trap : in std_logic;
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return_m_trap : in std_logic;
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mepc_in : in yarm_word;
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mcause_in : in yarm_trap_cause;
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mtval_in : in yarm_word;
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raise_exc : out std_logic;
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exc_data : out exception_data_t
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);
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end csr;
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@ -1,21 +0,0 @@
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entity decoder is
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port (
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clk : in std_logic;
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enable : in std_logic;
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async_addr_rs1 : out register_addr_t;
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async_addr_rs2 : out register_addr_t;
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alu_muxsel_a : out mux_selector_t;
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alu_muxsel_b : out mux_selector_t;
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alu_muxsel_cmp2 : out mux_selector_t;
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csr_muxsel_in : out mux_selector_t;
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instr_info_in : in instruction_info_t;
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instr_info_out : out instruction_info_t;
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raise_exc : out std_logic;
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exc_data : out exception_data_t
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);
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end decoder;
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@ -1,36 +0,0 @@
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entity exception_control is
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port (
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clk : in std_logic;
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fetch_raise_exc : in std_logic;
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fetch_exc_data : in exception_data_t;
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-- synchronous exceptions
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decoder_raise_exc : in std_logic;
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decoder_exc_data : in exception_data_t;
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csr_raise_exc : in std_logic;
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csr_exc_data : in exception_data_t;
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alignment_raise_exc : in std_logic;
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alignment_exc_data : in exception_data_t;
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datamem_raise_exc : in std_logic;
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datamem_exc_data : in exception_data_t;
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-- interrupts
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global_int_enabled : in std_logic;
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interrupts_enabled : in yarm_word;
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interrupts_pending : in yarm_word;
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-- stage inputs for return address + trap value (instruction)
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stage_inputs : in pipeline_frames_t;
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interrupted_stage : in pipeline_stage_t;
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may_interrupt : in std_logic;
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do_trap : out std_logic;
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trap_cause : out yarm_trap_cause;
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trap_address : out yarm_word;
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trap_value : out yarm_word
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);
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end exception_control;
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@ -1,16 +0,0 @@
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entity memctl is
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port (
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addr : in yarm_word;
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-- data width
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data_width : in datum_width_t;
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-- perfom sign extension when reading short data
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sign_extend : in std_logic;
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data_read : out yarm_word;
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data_write : in yarm_word;
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MEM_addr : out yarm_word;
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MEM_byte_enable : out std_logic_vector(3 downto 0);
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MEM_data_read : in yarm_word;
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MEM_data_write : out yarm_word
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);
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end memctl;
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@ -1,31 +0,0 @@
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entity memory_arbiter is
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port (
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clk : in std_logic;
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reset : in std_logic;
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fetch_enable : in std_logic;
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fetch_ready : out std_logic;
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fetch_address : in yarm_word;
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fetch_instr_out : out yarm_word;
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fetch_raise_exc : out std_logic;
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fetch_exc_data : out exception_data_t;
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datamem_enable : in std_logic;
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datamem_ready : out std_logic;
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datamem_instr_info_in : in instruction_info_t;
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datamem_read_data : out yarm_word;
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datamem_raise_exc : out std_logic;
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datamem_exc_data : out exception_data_t;
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-- little-endian memory interface, 4 byte address alignment
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MEM_addr : out yarm_word;
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MEM_read : out std_logic;
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MEM_write : out std_logic;
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MEM_ready : in std_logic;
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MEM_byte_enable : out std_logic_vector(3 downto 0);
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MEM_data_read : in yarm_word;
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MEM_data_write : out yarm_word
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);
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end memory_arbiter;
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@ -1,20 +0,0 @@
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entity multiplier is
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generic (
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-- A shorter than B: faster, but wider adder required
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WIDTH_A : positive;
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WIDTH_B : positive
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--PARALLELISM : positive
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);
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port (
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clk : in std_logic;
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run : in std_logic;
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valid : out std_logic;
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mul_signed : in std_logic;
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a : in std_logic_vector(WIDTH_A-1 downto 0);
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b : in std_logic_vector(WIDTH_B-1 downto 0);
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result : out std_logic_vector(WIDTH_A+WIDTH_B-1 downto 0)
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);
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end multiplier;
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@ -1,9 +0,0 @@
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entity program_counter is
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port (
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clk : in std_logic;
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reset : in std_logic;
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operation : in pc_operation_t;
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pc_in : in yarm_word;
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pc_out : out yarm_word
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);
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end program_counter;
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@ -1,16 +0,0 @@
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entity registers is
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port (
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clk : in std_logic;
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read_enable : in std_logic;
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write_enable : in std_logic;
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addr_a : in register_addr_t;
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addr_b : in register_addr_t;
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addr_d : in register_addr_t;
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data_a : out yarm_word;
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data_b : out yarm_word;
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data_d : in yarm_word
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);
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end registers;
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