diff --git a/sections/soc/soc.tex b/sections/soc/soc.tex
index 22d06fc..7eef8e9 100644
--- a/sections/soc/soc.tex
+++ b/sections/soc/soc.tex
@@ -56,6 +56,8 @@ While the Digilent board offers fewer IO options, the DDR3 memory can be interfa
 
 FPGA design is done using a Hardware Description Language (HDL). The two most well-known HDLs are Verilog and VHDL (VHSIC (Very high speed integrated circuit) HDL). As part of our studies at HTL, we exclusively worked with VHDL. For this reason, and because VHDL offers a strong type system~\cite{vhdl-types}, it was selected as the language of choice for the project.
 
+To refresh the reader's memory on the VHDL language, and as a quick guide for the tools involved in this project, see Appendix~\ref{app:vhdl-intro}.
+
 \subsection{Vendor Tools}
 
 The conventional way to work with FPGA designs is to use the FPGA vendor's development solution for simulation, synthesis and place-and-route. All of these tools are proprietary software specialized to a certain FPGA manufacturer, so a change of hardware also requires changing to a completely different software solution.
diff --git a/sections/vhdl_intro/vhdl_intro.tex b/sections/vhdl_intro/vhdl_intro.tex
index fd4d460..f3c905e 100644
--- a/sections/vhdl_intro/vhdl_intro.tex
+++ b/sections/vhdl_intro/vhdl_intro.tex
@@ -2,6 +2,7 @@
 \begin{document}
 
 \section{A short introduction to VHDL}
+\label{app:vhdl-intro}
 
 Designing a processor is a big task, and it's easiest to start very small. With software projects, this is usually in the form of a ``Hello World'' program - we will be designing a hardware equivalent of this.