From e65030ef47f683bb9d9349a244bbf3d806170f5b Mon Sep 17 00:00:00 2001
From: Xiretza <xiretza@xiretza.xyz>
Date: Fri, 27 Mar 2020 12:49:38 +0100
Subject: [PATCH] Add information about riscv compliance tests

---
 Diplomschrift.bib    |  6 ++++++
 sections/soc/soc.tex | 16 ++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/Diplomschrift.bib b/Diplomschrift.bib
index 371e8eb..d5cc914 100644
--- a/Diplomschrift.bib
+++ b/Diplomschrift.bib
@@ -71,3 +71,9 @@
 	title  = {GTKWave},
 	url    = {http://gtkwave.sourceforge.net},
 }
+
+@online{riscv-compliance,
+    author = {Jeremy Bennett, Lee Moore},
+    title  = {RISC-V Compliance Task Group},
+    url    = {https://github.com/riscv/riscv-compliance},
+}
diff --git a/sections/soc/soc.tex b/sections/soc/soc.tex
index 3dc5ac2..d0e2194 100644
--- a/sections/soc/soc.tex
+++ b/sections/soc/soc.tex
@@ -143,4 +143,20 @@ The exact timing differs between models, so all periods can be customized using
 
 % TODO
 
+\section{Testing}
+
+\subsection{RISC-V Compliance Tests}
+
+The RISC-V Compliance Test Suite\cite{riscv-compliance} can be used to empirically confirm the correct functionality of a RISC-V processor. It consists of a series of programs that perform some operations related to a specific feature, then write some result data to a memory region. This memory region is then compared to a ``golden signature'', which was produced by a processor implementation that is known to be correct.
+
+The initial implementation of the compliance tests uncovered several bugs in the processor core:
+
+\begin{itemize}
+ \item The bitshift instructions (SLL, SRL, SRA, etc.) must, according to the RISC-V standard, only use the lower 5 bits of the second operand as a shift offset. The implementation used all 31 bits instead, causing a test failure.
+ \item Reading a signed value of a size less than 32 bits from memory would not perform proper sign extension. For example, reading a byte value of 0xFF (-1) would result in an expanded machine word of 0x0000_00FF (255) instead of 0xFFFF_FFFF.
+ \item The \icode{SLTIU} (Set less than immediate; unsigned) instruction compares a given register with a constant provided as part of the instruction (the immediate). While the comparison is unsigned, the 12-bit immediate must be sign-extended as if it were a signed integer. The implementation wrongly assumed that the sign-extension should be unsigned as well.
+ \item The Instruction Set Manual specifies exceptions that must be raised when a misaligned memory access occurs. These exceptions were not yet implemented, but since the compliance tests check for them, the functionality was added to make the tests pass.
+\end{itemize}
+
+Since these tests are easily automated, they were added to the GitLab Continuous Integration (CI) configuration. Whenever a new git commit is pushed to GitLab, the tests are run automatically, and any failures are reported to the responsible committer via email.
 \end{document}