diff --git a/.gitignore b/.gitignore index b1e4424..d1dede4 100644 --- a/.gitignore +++ b/.gitignore @@ -13,7 +13,12 @@ *.out *.kate-swp +*.pdf_tex + *.o *.ghw *.gtkw work-*.cf + +svg-inkscape/ +core/entities/ diff --git a/Diplomschrift.bib b/Diplomschrift.bib index 8696878..d10cf11 100644 --- a/Diplomschrift.bib +++ b/Diplomschrift.bib @@ -1,19 +1,25 @@ @online{nandgame, - author = "Olav Junker Kjær", - title = "The Nand Game", - url = "http://nandgame.com", + author = {Olav Junker Kjær}, + title = {The Nand Game}, + url = {http://nandgame.com}, } @online{breadboard_computer, - author = "Ben Eater", - title = "Building an 8-bit breadboard computer!", - url = "https://www.youtube.com/playlist?list=PLowKtXNTBypGqImE405J2565dvjafglHU", - year = "2016", + author = {Ben Eater}, + title = {Building an 8-bit breadboard computer!}, + url = {https://www.youtube.com/playlist?list=PLowKtXNTBypGqImE405J2565dvjafglHU}, + year = {2016--2019}, } @unpublished{yosys, - author = "Clifford Wolf, Johann Glaser", - title = "Yosys - A Free Verilog Synthesis Suite", - url = "http://www.clifford.at/yosys/files/yosys-austrochip2013.pdf", - year = "2013", + author = {Clifford Wolf, Johann Glaser}, + title = {Yosys - A Free Verilog Synthesis Suite}, + url = {http://www.clifford.at/yosys/files/yosys-austrochip2013.pdf}, + year = {2013}, +} + +@software{liteeth, + author = {Florent Kermarrec}, + title = {LiteEth}, + url = {https://github.com/enjoy-digital/liteeth} } diff --git a/Diplomschrift.tex b/Diplomschrift.tex index f66dc47..93da7ea 100644 --- a/Diplomschrift.tex +++ b/Diplomschrift.tex @@ -17,6 +17,8 @@ \newpage \subfile{vhdl_intro/vhdl_intro.tex} +\subfile{soc/soc.tex} +\subfile{core/core.tex} \printbibliography diff --git a/core/core.tex b/core/core.tex new file mode 100644 index 0000000..5abc5e6 --- /dev/null +++ b/core/core.tex @@ -0,0 +1,72 @@ +\documentclass[../Diplomschrift.tex]{subfiles} + +\begin{document} + +\part{The Core} + +The core implements the \instrset{} architecture as specified by the RISC-V standard. + +It is constructed according to the traditional RISC pipeline: + +\begin{description} + \item[Fetch] fetches the next instruction from memory. + \item[Decode] decodes the instruction into its constituent parts. At the same time, operand values are loaded from any required registers. + \item[Execute] performs the action required by the instruction, such as math performed by the Arithmetic Logic Unit (ALU) or writing to Control and Status Registers (CSRs). + \item[Memory] loads values from or stores values to the system's main memory or interacts with memory-mapped hardware devices. + \item[Writeback] stores a potential result value from Execute or Memory stages to the destination register. +\end{description} + +\section{Overview} + +\includegraphics[width=\textwidth]{core_diagram.png} + +\section{Control} + +\entityheader{entities/control_entity.vhd}{control.vhd} + +The control unit is responsible for coordinating subcomponents and the data flow between them. Internally, it is based on \icode{instruction\_info\_t} structures, which contain all the information required to pass an instruction along the different pipeline stages. Before the fetch stage, when an instruction is first scheduled, it contains only the instruction's address (because nothing else is known about it). Then, information is added incrementally by the different stages. + +\section{Decoder} + +\entityheader{entities/decoder_entity.vhd}{decoder.vhd} + +The decoder receives an instruction and interprets it. Among others, it determines + +\begin{itemize} + \item The source and destination register addresses + \item The pipeline stages that need to be run for the instruction + \item The ALU operation, if any + \item Whether the instruction should branch, and if so, under what condition +\end{itemize} + +\section{Registers} + +\entityheader{entities/registers_entity.vhd}{registers.vhd} + +The registers store the 32 general-purpose values required by \instrset{} (each 32-bit wide). They are accessible through two read ports and one write port. As specified by the RISC-V standard, the first register (\icode{x0}) is hard-wired to 0, and any writes to it are ignored. + +\section{Arithmetic and Logic Unit (ALU)} + +\entityheader{entities/alu_entity.vhd}{alu.vhd} + +The ALU contains a math/logic unit as well as a comparator. It is used both explicitly by instructions such as \icode{add} or \icode{shiftl}, as well as to add offsets to base addresses for memory instructions and to decide whether an instructions should branch. + +\section{Control and Status Registers (CSR)} + +\entityheader{entities/csr_entity.vhd}{csr.vhd} + +The control and status registers contain configurations relevant to the core itself. For example, they can be used to control interrupts. + +\section{Memory Arbiter} + +\entityheader{entities/memory_arbiter_entity.vhd}{memory\_arbiter.vhd} + +Since both fetch and memory stages need to access the same system memory, access to this common resource has to be controlled. The memory arbiter acts as a proxy for both fetch and data memory requests and stalls either until the other one completes. + +\section{Exception Control} + +\entityheader{entities/exception_control_entity.vhd}{exception\_control.vhd} + +Several components in the core may raise a synchronous exception when an unexpected error (such as a malformed instruction or an unaligned memory access) occurs. Additionally, asynchronous interrupts (like from a timer or a UART) can be triggered externally. When an exception or an enabled interrupt is registered, program flow is diverted to the trap handler, defined using the machine trap vector (\icode{mtvec}) CSR. + +\end{document} diff --git a/core/core_diagram.drawio b/core/core_diagram.drawio new file mode 100644 index 0000000..1d26d4a --- /dev/null +++ b/core/core_diagram.drawio @@ -0,0 +1 @@ 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\ No newline at end of file diff --git a/core/core_diagram.png b/core/core_diagram.png new file mode 100644 index 0000000..46a770e Binary files /dev/null and b/core/core_diagram.png differ diff --git a/preamble.tex b/preamble.tex index 0df6cb9..f93a307 100644 --- a/preamble.tex +++ b/preamble.tex @@ -2,6 +2,7 @@ \usepackage{graphicx} \usepackage{url} \usepackage{listings} +\usepackage{svg} \lstdefinelanguage{customvhdl}[]{VHDL}{ morekeywords=[2]{std_logic, std_logic_vector, natural, integer, bit, string}, @@ -43,6 +44,7 @@ \yyyymmdddate \renewcommand{\dateseparator}{-} +\usepackage{titlesec} \usepackage{fancyhdr} \usepackage{pst-uml} @@ -56,10 +58,37 @@ \setlength{\topmargin}{0pt} \addtolength{\voffset}{-1em} -\setlength{\parindent}{0px} +\setlength{\parindent}{0pt} \setlength{\parskip}{1em} \usepackage{footnote} +\usepackage{tikz} + +\newcommand\instrset{rv32i} + +\newcommand{\entityheader}[2]{ + \lstinputlisting[title=\texttt{#2}]{#1} +} + +\usepackage{tcolorbox} + +\newtcbox{\codeBox}[1][gray]{ + on line, + arc=2pt, + colback=black!5, + colupper=black!80, + colframe=black!20, + before upper={ + \rule[-3pt]{0pt}{10pt} + }, + boxrule=1pt, + boxsep=0pt, + left=3pt, + right=3pt, + top=2pt, + bottom=0pt +} +\newcommand{\icode}[1]{\codeBox{\texttt{#1}}} % loaded last \usepackage{hyperref} diff --git a/soc/Diplomschrift.bib b/soc/Diplomschrift.bib new file mode 120000 index 0000000..71b2fde --- /dev/null +++ b/soc/Diplomschrift.bib @@ -0,0 +1 @@ +../Diplomschrift.bib \ No newline at end of file diff --git a/soc/graphics.drawio b/soc/graphics.drawio new file mode 100644 index 0000000..1910f4d --- /dev/null +++ b/soc/graphics.drawio @@ -0,0 +1 @@ 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\ No newline at end of file diff --git a/soc/graphics.png b/soc/graphics.png new file mode 100644 index 0000000..a6ef262 Binary files /dev/null and b/soc/graphics.png differ diff --git a/soc/soc.tex b/soc/soc.tex new file mode 100644 index 0000000..5f81d07 --- /dev/null +++ b/soc/soc.tex @@ -0,0 +1,122 @@ +\documentclass[../Diplomschrift.tex]{subfiles} + +\begin{document} + +\part{Meta} +\section{History} + +The project started out with the desire to build a CPU from scratch. Examples such as The NAND Game\cite{nandgame} and Ben Eater's Breadboard Computer series\cite{breadboard_computer} served as inspirations and guidance during development. + +At first, a design similar to Ben Eater's consisting solely of discrete integrated circuits was considered, but soon discarded in favor of an FPGA-based design. Designing the logic alone was a difficult task, implementing it in discrete hardware would have pushed the project far over the allotted maximum development time. + +RISC-V was chosen as the instruction set architecture for the processor. Its modular design with a very small base instruction set make it easy to implement a basic processor that is still fully compatible with existing software and toolchains. + +As a starting point, a Terasic DE0 development board\footnote{\url{https://www.terasic.com.tw/cgi-bin/page/archive.pl?No=364}} containing an Altera Cyclone III\footnote{\url{https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iii.html}} FPGA was borrowed from the school's inventory. It was used to implement a first version of the core. + +The only method of synthesis for Altera devices is to use the proprietary Quartus IDE. However, the last version of Quartus to support the Cyclone III series of FPGAs (version 13.1) had already been out of date for several years at the start of the project. Because of this and the increasing resource demand of the developing core, an Arty A7-35T development board\footnote{\url{https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/}} with a Xilinx Artix-7\footnote{\url{https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html}} FPGA was ordered from Digilent. + +The two FPGAs compare as follows: + +\begin{tabular}{l r r} + & Altera EP3C16 & Xilinx XC7A35T \\ +Logic Elements & 15000 & 33280 \\ +Multipliers & 56 & 90 \\ +Block RAM (kb) & 504 & 1800 \\ +PLLs & 4 & 5 \\ +Global clocks & 20 & 32 \\ +\end{tabular} + +The periphery on the development boards: + +\begin{tabular}{l|r|r} + & Terasic DE0 & Digilent Arty A7-35T \\ +Switches & 10 & 4 \\ +Buttons & 3 & 4 \\ +LEDs & 10 + 4x 7-segment & 4 + 3 RGB \\ +GPIOs & 2x 36 & 4x PMOD + chipKIT \\ +Memory & 8MB SDRAM & 256MB DDR3L \\ +Others & SD card, VGA & Ethernet \\ +\end{tabular} + +While the Digilent board offers fewer IO options, the DDR3 memory can be interfaced using Free memory cores and allows for much larger programs to be loaded, possibly even a full operating system. The missing VGA port has been substituted by a HDMI-compatible DVI interface that is accessible through one of the high-speed PMOD connectors. + +\section{Tooling} + +FPGA design is done using a Hardware Description Language (HDL). The two most well-known HDLs are Verilog and VHDL (VHSIC (Very high speed integrated circuit) HDL). As part of our studies at HTL, we exclusively worked with VHDL. For this reason, and because VHDL offers a better type system, it was chosen as the language of choice for the project. + +\subsection{Vendor Tools} + +The conventional way to work with FPGA designs is to use the FPGA vendor's development solution for simulation, synthesis and place-and-route. All of these tools are proprietary software specialized to a certain FPGA manufacturer, so a change of hardware also requires changing to a completely different software solution. + +Vendor tools are usually free-of-charge for basic usage, but this also means there is no guaranteed support. During the development of this project, several bugs and missing features were found in vendor tools that required workarounds. + +\subsection{Free Software Tools} + +A somewhat recent development is the creation of Free Software\footnotemark FPGA toolchains. A breakthrough was achieved by Claire (formerly Clifford) Wolf in 2013 with yosys\cite{yosys}, a feature-complete Verilog synthesis suite for Lattice's \texttt{iCE40} FPGA series. + \footnotetext{``Free Software'' refers to software that grants its user the freedom to share, study and modify it - see \url{https://www.fsf.org/about/what-is-free-software}.} +Since then, both yosys and place-and-route tools like nextpnr\footnote{\url{https://github.com/YosysHQ/nextpnr}} have matured, however Lattice's iCE40 and ECP5 remained the only supported FPGA architectures for place-and-route. + +Thus, two obstacles remained for Free toolchains to be viable for this project: synthesizing from VHDL code and synthesizing to Artix-7 FPGAs. During the development of the project, both of these were solved: Tristan Gingold released \texttt{ghdlsynth-beta}\footnote{\url{https://github.com/tgingold/ghdlsynth-beta}}, a bridge between GHDL and yosys allowing VHDL to be synthesized just the same as Verilog, and Dave Shah added Xilinx support to nextpnr. The latter was preceded by many months of volunteer work reverse-engineering the Xilinx bitstream format as part of \textit{Project X-Ray}\footnote{\url{https://symbiflow.github.io/prjxray-db/}}. + +With these two pieces in place, the project was switched over to a completely Free toolchain, removing any depencies on vendor tools: + +\begin{itemize} + \item yosys, with ghdl as a frontend for processing VHDL, is used to synthesize the design + \item nextpnr-xilinx, together with the Project X-Ray database, is used for place-and-route + \item tools from Project X-Ray are used to convert the routed design to a bitstream + \item xc3sprog is used to transfer the bitstream to the FPGA via JTAG +\end{itemize} + +\section{Peripherals} + +\subsection{UART} + +% TODO + +\subsection{DVI graphics} + +The graphics submodule consists of a VGA timing generator, a text renderer with a font ROM, and a DVI encoder frontend: + +\includegraphics[width=\textwidth]{graphics.png} + +\subsubsection{VGA timing} + +The timing of VGA signals dates back to analog monitors. Even though this original purpose is only very rarely used nowadays, the timing remained the same for analog and digital DVI all the way to modern HDMI. + +In analog screens, the electron beams (one for each primary color red, green and blue) scan across the screen a single horizontal line at a time while being modulated by the color values, resulting in a continuous mixture of all three components. When a beam reaches the end of a scanline, it continues outside the visible area for a small distance (the ``Front Porch''), is then sent to the beginning of the next line by a pulse of the hsync (Horizontal Sync) signal, and draws the next line after another short off-screen period (the ``Back Porch''). + +The same applies to vertical timings: after the beam reaches the end of the last line, a few off-screen Front Porch lines follow, then a pulse of the vsync (Vertical Sync) signal sends the beam to the top of the screen, where the first line of the next frame is drawn after several invisible Back Porch lines. + +\begin{center} +\includegraphics[width=\textwidth]{vga_timing.png} +\end{center} + +The VGA timing module generates these hsync and vsync signals, along with a blanking signal (active during any front porch, sync and back porch) and, while in the visible area (i.e. not blanking), the row and column of the current pixel relative to the visible area. + +\subsubsection{Text renderer} + +The text renderer converts a logical representation of a character, such as its ASCII code (henceforth referred to as its \textit{codepoint}) to a visual representation (a \textit{glyph}). This conversion is achieved using a \textit{font}, a mapping of codepoints to glyphs. + +\begin{center} +\includegraphics[width=0.7\textwidth]{text_renderer.png} +\end{center} + +First, the current pixel coordinate (created by the VGA timing generator) is split up into two parts: the character index, which specifies the on-screen character the pixel belongs to, and the offset of the pixel in this character. The character index is passed to the text RAM, which contains the codepoint for each on-screen character. This codepoint, along with the pixel offset, is looked up in the font ROM to determine the color of the pixel. + +\subsubsection{TMDS encoder} + +DVI and HDMI are serial digital transmission standards. Three data lines (corresponding to red, green, and blue channels) along with a clock line transmit all color information as well as synchronization signals. The encoding used for these signals is Transition-minimized differential signaling (TMDS). It is a kind of 8b/10b encoding (transforming every 8-bit chunk of data into a 10-bit chunk) that is designed to minimize the number of changes of the output signal. + +\subsection{Ethernet} + +The Arty development board contains an RJ-45 Ethernet jack connected to an Ethernet PHY, which exposes a standardized media-independent interface (MII) to the FPGA. The LiteEth core\cite{liteeth}, which is released under a Free Software license, is used to integrate the Ethernet interface into the SoC. + +\subsection{WS2812 driver} + +% TODO + +\subsection{DRAM} + +% TODO + +\end{document} diff --git a/soc/text_renderer.drawio b/soc/text_renderer.drawio new file mode 100644 index 0000000..5dc4cfe --- /dev/null +++ b/soc/text_renderer.drawio @@ -0,0 +1 @@ +1VnLkusmEP0aL3NLEpIsLT2vZJGpTM2kbnJXKSxhiQQLFcJjeb4+INAD4fFYFT/ijQuapoHD6UPbnoH7df0zg2X+TFNEZp6T1jPwMPO8eeCIT2nYKYMPfGXIGE6Vye0Nb/gDaaOel21wiirDkVNKOC5NY0KLAiXcsEHG6NZ0W1FirlrCDFmGtwQS2/oHTnmuraHj9AO/IJzleum4HVjD1lkbqhymdDswgccZuGeUctVa1/eISOxaXNS8p09Gu40xVPBjJlTP3xd/rfJnz9mGy5dwVX9/ff0p0Hvju/bAKBXn111ElnT72BvuGN0UKZIBHdGjjOc0owUkv1JaCqMrjH8jznf6HuGGU2HK+ZroUVRj/qec/m0e6O4PHU22H+phZ6c7FWf0nw7+UA4XnO2GcWT/R7uG7PSRml4bSh1XnvFTFLWpohuWoAPQeZqNkGWIH/CLursWOYLoGon9iHkMEcjxu7kPqNmadX7d1BeKxQ49RyeW39Jq1zHSDKH2pWf1tFgwBncDt1I6VJ+vAyJznRHLRENFbHuDM/amhokTWNkm/+Vo2fPJm8SnPdTsGB4OCO5+AwcpLjsviGGBHGKn56obXJWs3nxEVj8wQ6gDTCDrgH8nYVyH5H7G9ZQ6kxp6/0UNV7Tgeo14RGbXG7JZrhN/weimN6ZiJYjDF/I5FYaEwKrCSWt+wqRPo7R1KmiBlEWPX0l9XXAWRruxyWj/TOoLIlN9g9B846f5n0et9VW8Q7LRcP6Oarmp18WzlVVmzmxzzNFbCZur3ooC0swPRfV7SihrZoMwidByJSkvSDWwpxBFq6Rj2DtiHNWHOWZTosXQDU0M2xdw29d/7e3ng8pv/AAPSWTI1VR8w9us0U6Y7OfJ4dCPR6+Sf5YkDsavXzAq1L/yjyf6R9P8PXCBkg5YIvFEm029/naLIuGPy+I9IuF6l1SJ+GoqcbxIfFpm92XIsWX2CdUlOrKUOIkKTRYP9wrfvyIrWS1yVTksZZOLfEQfVIa7KwdVY2cflJJfZbLJyel5zSgXN0ELWQc7J8pzd792D/M83JPm3rnS3LWF9BLyqcv5EyBqfRd0bUTBPuV0QXAuTH0L04SmqOwe/iG4XNa2BoKQ4ExyLhEINDSX+OAEkoUeWOM0VaKLKvwBl00oeTU6+UXc4G4WPMhYQmcrJbnuicrZ+aicbUMM8J5flMGBhXaJ6+ZX44RSluICcnTzsLsWzWO7QHAuint4AHeZ5bcOeRCDEeTgykyfW4ivVNFLaKJeqlvH3AeeqS6OrS7RRTG3a5ckhwwmEjwvJBLdpWxlsoXFO1lPuASmTvD/ugMvNHkviH8U78H0OxDd/g8rVW32//qBx38B \ No newline at end of file diff --git a/soc/text_renderer.png b/soc/text_renderer.png new file mode 100644 index 0000000..c36083a Binary files /dev/null and b/soc/text_renderer.png differ diff --git a/soc/vga_timing.png b/soc/vga_timing.png new file mode 100644 index 0000000..434b028 Binary files /dev/null and b/soc/vga_timing.png differ diff --git a/vhdl_intro/vhdl_intro.tex b/vhdl_intro/vhdl_intro.tex index f27b7e7..ce3c35d 100644 --- a/vhdl_intro/vhdl_intro.tex +++ b/vhdl_intro/vhdl_intro.tex @@ -11,10 +11,10 @@ Other than a text editor, the following Free Software packages have to be instal \begin{savenotes} \begin{description} - \item[\texttt{ghdl}\footnote{\url{https://github.com/ghdl/ghdl}}] to compile and simulate the design - \item[\texttt{gtkwave}\footnote{\url{http://gtkwave.sourceforge.net/}}] to view the generated waveform files - \item[GNU \texttt{make}] to coordinate simulating designs, compiling firmware and generating images - \item[python] for helper scripts + \item[\icode{ghdl}\footnote{\url{https://github.com/ghdl/ghdl}}] to compile and simulate the design + \item[\icode{gtkwave}\footnote{\url{http://gtkwave.sourceforge.net/}}] to view the generated waveform files + \item[GNU \icode{make}] to coordinate simulating designs, compiling firmware and generating images + \item[\icode{python}] for helper scripts \end{description} \end{savenotes}