Added more parts to the DS

von neumann was a genius really...

Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
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Tyrolyean 2020-03-29 00:03:46 +01:00
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@ -29,6 +29,17 @@
volume = {1997} volume = {1997}
} }
@techreport{neumann,
type = {Report},
key = {W670ORD4926},
month = Jun,
year = {1945},
title = {First Draft of a Report on the EDVAC},
institution = {United States Army Ordnance Department and the University of Pennsylvania},
volume = {1945},
url = {http://abelgo.cn/cs101/papers/Neumann.pdf}
}
@Manual{max232, @Manual{max232,
month = Feb, month = Feb,
year = {1989}, year = {1989},

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@ -20,6 +20,29 @@ layout of the Atari Parallel Bus Interface is shown as used on the Atari 800XL.
\label{fig:atari_pbi} \label{fig:atari_pbi}
\end{figure} \end{figure}
\paragraph{System Bus}
In some architectures the backbone parallel bus consisting of data- address- and
control bus is called the system bus. The system bus even has its own wikipedia
article \footnote{\url{https://en.wikipedia.org/wiki/System_bus}} and the
picture seen in
figure \ref{fig:sysbus}, which has been taken from this wikipedia article, even
shows the exact same parts. However the origin of this term could not be
determined and its use was the most common when describing the interface between
the fabric of the CPU with external parts via this interface on a motherboard,
which ran on system clock speed and was synchronized with the processor.
The term parallel bus was chosen for this thesis because the bus runs on an
independant clock speed and only interacts with the processor asynchronous to
its clock. The term front side bus would be more fitting but not used because of
its affiliation with intel products.
\begin{figure}[H]
\includesvg[width=\textwidth, angle=0]{pics/sysbus}
\caption{System bus structural diagram; Source: \url{https://en.wikipedia.org/}}
\label{fig:sysbus}
\end{figure}
\subsubsection{Address Bus} \subsubsection{Address Bus}
The address bus contains the nescessary data lines for addressing the individual The address bus contains the nescessary data lines for addressing the individual
@ -73,3 +96,41 @@ to the data bus.
A low level on one of these lines signals the corresponding module that the A low level on one of these lines signals the corresponding module that the
data on address data and the control lines is meant for it. data on address data and the control lines is meant for it.
\subsection{Von Neumann Archtiecture}
The term ``von Neumann architecture`` referrs to a type of computer architecture
which referres to almost any modern computer system. It describes the in this
thesis used Human input and output parts and the general workings of modern
processors with the ALU\footnote{ALU...arithmetic logic unit} or the CA
\footnote{CA...Central Arithmetic Part} as well as means to interface with its
operator\cite{neumann}.
In his thesis ``First Draft of a Report on the EDVAC`` he writes about human
input:
\vspace{1cm}
``Once these instructions are given to the device, it must be able to carry them out completely and
without any need for further intelligent human intervention. At the end of the required operations
the device must record the results again in one of the forms referred to above.``\cite[p.7]{neumann}
\vspace{1cm}
This can be applied to the hardware implemented in this thesis, as well as
other general computing systems. The EDVAC, which his thesis referres to, was a
computer developed for military purposes. Much like the EDVAC, the CPU in this
thesis is responsible for arithemtic operations and code interpetation. The
peripherials are what is referred to as the input and output devices in his
report. Though the for examples used ATMega2650 utilizes a harvard architecture
``In order to maximize performance and parallellism``\cite[p.11]{atmega2560} the
more general descriptions of computational operations still apply to this
thesis. The differences between a harvard architecture and a von neumann
architecture are shown in figure \ref{fig:harvard_neumann}
\begin{figure}[H]
\includesvg[width=.5\textwidth, angle=0]{pics/harvard}
\includesvg[width=.5\textwidth, angle=0]{pics/neumann}
\caption{Harvard(left) vs Von-Neumann architecture(right);\\
Source: \url{https://en.wikipedia.org/}}
\label{fig:harvard_neumann}
\end{figure}

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@ -160,6 +160,21 @@ modern CD Drives, an ASIC
with an internal PLL is used, thus the required quartz can no longer be sourced with an internal PLL is used, thus the required quartz can no longer be sourced
via conventional electronic resellers. via conventional electronic resellers.
\subsubsection{DAC Module Read}
On a read the status bits of the FIFO, which have been latched into the 74HC374
D-Flip-Flop, are written onto the Data bus. Table \ref{tab:dac_data}
\begin{table}[H]
\centering
\begin{tabular}{ c | r |}
\end{tabular}
\caption{The layout of the Data Bus on read}
\label{tab:dac_data}
\end{table}
\subsubsection{Demonstration Software} \subsubsection{Demonstration Software}
\paragraph{SAW Generator} \paragraph{SAW Generator}

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@ -79,3 +79,16 @@ diodes produce the 0.7V offset and prevent the parallel bus from rising to
\caption{The internal clamping diodes of the Analog Discovery 2\cite{ad2}} \caption{The internal clamping diodes of the Analog Discovery 2\cite{ad2}}
\label{fig:ad2_diode} \label{fig:ad2_diode}
\end{figure} \end{figure}
\subsubsection{Final Module}
The final module can be seen in figure \ref{fig:fpga_mod} without the FPGA
attached. The blue modules below are the level shifters.
\begin{figure}[H]
\centering
\includegraphics[width=\textwidth, angle=0]{pics/fpga_int}
\caption{The final FPGA interface module with the level shifters}
\label{fig:fpga_mod}
\end{figure}