Language improvements

sections/abstract.tex

@@ -6,7 +6,7 @@ anschaulich den
 Aufbau eines Computersystems in Hard- und Software zu veranschaulichen
 sowie diesen zu erklären. Dafür wurde auf einem XILINX FPGA ein RISC-V32I 
 Prozessor in VHDL
-implementiert sowie diverse Parallelbus gebundene Hardwareperipherie entwickelt
+implementiert, sowie diverse Parallelbus-gebundene Hardwareperipherie entwickelt
 und gebaut. Als Harwareperipherie wurde ein 8-Bit 2-Kanal DAC und eine serielle
 Schnittstelle mit TIA-/EIA-232 Pegeln gewählt. Der Prozessor implementiert das
 RISC-V32I base instruction set. Aufgrund der starken Verwendung von Englisch im
@@ -17,14 +17,14 @@ Menschen mit einem grundlegenden Verständnis für Elektronik sowie der Hardware
 Beschreibungssprache VHDL verständlich sein.
 \end{otherlanguage}
 \\\\
-This diploma thesis deals with the operation of processors and their 
-corresponding peripherals in modern and traditional forms. It attempts to
+This diploma thesis demonstrates the operation of processors and their 
+corresponding peripherals, both in modern and traditional forms. It attempts to
 illustrate the structure of a computer system in hard- and software. To reach
-this goal a RISC-V32I processor has been implemented in VHDL on a XILINX FPGA
-as well as some peripherals bound to the parallel bus. These peripherals
-include a 2-channel 8-bit Digital to analog converter as well as a TIA-/EIA-232
+this goal, a RISC-V processor was implemented in VHDL on a Xilinx FPGA and some
+parallel bus peripherals were designed using discrete hardware. These peripherals
+include a 2-channel 8-bit digital-to-analog converter as well as a TIA-/EIA-232
 compliant serial interface. Due to the common use of english in the hardware and
-software engineering field this thesis is written in english, which
-enhances readability as well. The written documentation should be comprehensible
-for everyone with a basic understanding of electronics as well as the
+software engineering field, and in a resulting effort to increase readability,
+this thesis is written in English. The written documentation should be comprehensible
+for anyone with a basic understanding of electronics as well as the
 hardware description language VHDL.

sections/intro.tex

@@ -1,22 +1,23 @@
 In early 2018, more than a year before the official start of the project, after
 searching for a subject for the diploma thesis, the idea of building a computer
-from scratch has come up. Multiple suggestions on how to implement it and the
-scope of the project were gathered. Originally the goal of the project was to
-have a computer which would consist of seperate plug-in cards on each of which
-one instruction would reside. This would debunk the mystery behind the ``black
-box`` which processors are today.
+from scratch had come up. Multiple suggestions on how to implement it and the
+scope of the project were gathered. Originally, the goal was to
+design a computer consisting of seperate plug-in cards, one instruction would
+residing on each. This would open up the ``black box`` of modern processor
+design, showing the basic components at a macroscopic scale.
 
-Most processors today are only documented on the execution of their programs and
-not on their internals. The projects aim was later redirected, due to concerns
-about the difficulty of the project, to build a processor in VHDL instead. After
-several months of implementation time the project was split into two parts: the
-peripherals and the core processor. During the development processes and after
-rememberingthe original goal to make a processor understandable, the
-peripherals changed from being implemented in VHDL back to hardware, which came
-with increased work but would result in a far more understandable final product.
-
-The decision for a RISC-V based processor was made at the beginning of the 
-project, because the core architecture is well documented, modular and almost
-any part not implemented inside the processor(if not specifically
-required by the software) should be emulateable in software.
+For most of today's processors, documentation only exists for the execution of
+programs (the runtime), not for their internals. The project's aim was later
+redirected due to concerns about difficulty, and an FPGA-based design was opted
+for instead. After
+several months of implementation time, the project was split into two parts: the
+peripherals and the core processor. During the development process, and to get
+back to the original goal of making a processor understandable, the
+peripherals changed from being implemented in VHDL back to hardware.
+This increased the required effort, but would result in a far more
+understandable final product.
 
+The decision to use a RISC-V based processor was made at the beginning of the 
+project because the core architecture is well documented and modular, and because
+almost any feature not implemented inside the processor can be emulated using
+software instead.

sections/result.tex

@@ -1,12 +1,13 @@
 The project is fully implemented with all functionality originally targeted.
-The system has been tested and verified. All example codes have been
+The system has been tested and verified. All example code has been
 documented and tested. Hardware implementations were created using
-Free software programs, while the RISC-V processor can be compiled with a Free
-toolchain. The completed project can be found on the USB stick, which accompanies
+Free software\footnote{See \autoref{sec:free-software}} programs, while the
+RISC-V processor can be compiled with a Free
+toolchain. The completed project can be found on the USB stick which accompanies
 this thesis, or in the git repositories at 
 \url{https://git.it-syndikat.org/tyrolyean/dipl.git} and 
 \url{https://gitlab.com/YARM-project/}. The completed hardware peripherals can
-be seen in Figure \ref{fig:all_mod}
+be seen in \autoref{fig:all_mod}.
 
 \begin{figure}[H]
 	\centering