Move FPGA development section to separate file

main.tex

@@ -132,8 +132,9 @@ geschlechtsunabh"angig verstanden werden soll.
 \DP\input{sections/DP/textadv/main.tex}
 \clearpage
 
-\AB\subfile{sections/soc/soc.tex}
+\AB\subfile{sections/fpga-development.tex}
 \AB\subfile{sections/core/core.tex}
+\AB\subfile{sections/soc/soc.tex}
 
 %====================================================================================
 \allAuth

sections/fpga-development.tex

@@ -0,0 +1,81 @@
+\documentclass[../../Diplomschrift.tex]{subfiles}
+
+\begin{document}
+\section{FPGA Development}
+
+The project started out with the desire to build a CPU from scratch. Examples such as The NAND Game~\cite{nandgame} and Ben Eater's Breadboard Computer series~\cite{breadboard_computer} served as inspirations and guidance during development.
+
+At first, a design similar to Ben Eater's, consisting solely of discrete integrated circuits, was considered, but soon discarded in favor of an FPGA-based design. Designing the logic alone was a difficult task, implementing it in discrete hardware would have pushed the project far over the allotted maximum development time.
+
+RISC-V was chosen as the instruction set architecture for the processor. Its modular design with a very small base instruction set makes it easy to implement a basic processor that is still fully compatible with existing software and toolchains.
+
+As a starting point, a Terasic DE0 development board\footnote{\url{https://www.terasic.com.tw/cgi-bin/page/archive.pl?No=364}} containing an Altera Cyclone III\footnote{\url{https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iii.html}} FPGA was borrowed from the school's inventory. It was used to implement a first version of the core.
+
+The only method of synthesis for Altera devices is to use the proprietary Quartus IDE. However, the last version of Quartus to support the Cyclone III series of FPGAs (version 13.1) had already been out of date for several years at the start of the project. Because of this and the increasing resource demand of the developing core, an Arty A7-35T development board\footnote{\url{https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/}} with a Xilinx Artix-7\footnote{\url{https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html}} FPGA was ordered from Digilent.
+
+A comparison between the two FPGAs themselves can be seen in \autoref{tab:fpga-comparison}, a comparison between the peripherals on the development boards in \autoref{tab:devboard-comparison}.
+
+\begin{table}[h]
+\centering
+\begin{tabular}{l|r|r}
+\toprule
+               & Altera EP3C16 & Xilinx XC7A35T \\
+\midrule
+Logic Elements & 15000 & 33280 \\
+Multipliers    &    56 &    90 \\
+Block RAM (kb) &   504 &  1800 \\
+PLLs           &     4 &     5 \\
+Global clocks  &    20 &    32 \\
+\bottomrule
+\end{tabular}
+\caption{Comparison between Altera and Xilinx FPGAs}
+\label{tab:fpga-comparison}
+\end{table}
+
+\begin{table}[h]
+\centering
+\begin{tabular}{l|r|r}
+\toprule
+         & Terasic DE0 & Digilent Arty A7-35T \\
+\midrule
+Switches &           10 & 4 \\
+Buttons  &            3 & 4 \\
+LEDs     & 10 + 4x 7-segment & 4 + 3 RGB \\
+GPIOs    &        2x 36 & 4x PMOD + chipKIT \\
+Memory   &    8MB SDRAM & 256MB DDR3L \\
+Others   & SD card, VGA & Ethernet \\
+\bottomrule
+\end{tabular}
+\caption{Comparison between the peripherals on Terasic and Digilent FPGA development boards}
+\label{tab:devboard-comparison}
+\end{table}
+
+While the Digilent board offers fewer IO options, the DDR3 memory can be interfaced using Free memory cores and allows for much larger programs to be loaded, possibly even a full operating system. The missing VGA port has been substituted by an HDMI-compatible DVI interface that is accessible through one of the high-speed PMOD connectors.
+
+\subsection{Tooling}
+
+FPGA design is done using a Hardware Description Language (HDL). The two most well-known HDLs are Verilog and VHDL (VHSIC (Very high speed integrated circuit) HDL). As part of our studies at HTL, we exclusively worked with VHDL. For this reason, and because VHDL offers a strong type system~\cite{vhdl-types}, it was selected as the language of choice for the project.
+
+To refresh the reader's memory on the VHDL language, and as a quick guide for the tools involved in this project, see Appendix~\ref{app:vhdl-intro}.
+
+\subsubsection{Vendor Tools}
+
+The conventional way to work with FPGA designs is to use the FPGA vendor's development solution for simulation, synthesis and place-and-route. All of these tools are proprietary software specialized to a certain FPGA manufacturer, so a change of hardware also requires changing to a completely different software solution.
+
+Vendor tools are usually free-of-charge for basic usage, but this also means there is no guaranteed support. During the development of this project, several bugs and missing features were found in vendor tools that required workarounds.
+
+\subsubsection{Free Software Tools}
+
+A somewhat recent development is the creation of Free Software FPGA toolchains. A breakthrough was achieved by Claire (formerly Clifford) Wolf in 2013 with yosys~\cite{yosys-paper, yosys}, a feature-complete Verilog synthesis suite for Lattice's \texttt{iCE40} FPGA series. Since then, both yosys and place-and-route tools like nextpnr~\cite{nextpnr} have matured, however Lattice's iCE40 and ECP5 remained the only supported FPGA architectures for place-and-route.
+
+Thus, two obstacles remained for Free toolchains to be viable for this project: synthesizing \emph{from} VHDL code and synthesizing \emph{to} Artix-7 FPGAs. During the development of the project, both of these were solved: Tristan Gingold released ghdlsynth-beta~\cite{ghdlsynth-beta}, a bridge between GHDL~\cite{ghdl} and yosys allowing VHDL to be synthesized just the same as Verilog, and Dave Shah added Xilinx support to nextpnr~\cite{nextpnr-xilinx}. The latter was preceded by many months of volunteer work reverse-engineering the Xilinx bitstream format as part of \textit{Project X-Ray}~\cite{prjxray}.
+
+With these two pieces in place, the project was switched over to a completely Free toolchain, removing any depencies on vendor tools:
+
+\begin{itemize}
+ \item yosys, with ghdl as a frontend for processing VHDL and ghdlsynth as a bridge between them, is used to synthesize the design
+ \item nextpnr-xilinx, together with the Project X-Ray database, is used for place-and-route
+ \item tools from Project X-Ray are used to convert the routed design to a bitstream
+ \item openFPGALoader is used to transfer the bitstream to the FPGA via JTAG
+\end{itemize}
+\end{document}

sections/soc/soc.tex

@@ -1,86 +1,6 @@
 \documentclass[../../Diplomschrift.tex]{subfiles}
 
 \begin{document}
-\section{FPGA Development}
-
-The project started out with the desire to build a CPU from scratch. Examples such as The NAND Game~\cite{nandgame} and Ben Eater's Breadboard Computer series~\cite{breadboard_computer} served as inspirations and guidance during development.
-
-At first, a design similar to Ben Eater's consisting solely of discrete integrated circuits was considered, but soon discarded in favor of an FPGA-based design. Designing the logic alone was a difficult task, implementing it in discrete hardware would have pushed the project far over the allotted maximum development time.
-
-RISC-V was chosen as the instruction set architecture for the processor. Its modular design with a very small base instruction set make it easy to implement a basic processor that is still fully compatible with existing software and toolchains.
-
-As a starting point, a Terasic DE0 development board\footnote{\url{https://www.terasic.com.tw/cgi-bin/page/archive.pl?No=364}} containing an Altera Cyclone III\footnote{\url{https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iii.html}} FPGA was borrowed from the school's inventory. It was used to implement a first version of the core.
-
-The only method of synthesis for Altera devices is to use the proprietary Quartus IDE. However, the last version of Quartus to support the Cyclone III series of FPGAs (version 13.1) had already been out of date for several years at the start of the project. Because of this and the increasing resource demand of the developing core, an Arty A7-35T development board\footnote{\url{https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/}} with a Xilinx Artix-7\footnote{\url{https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html}} FPGA was ordered from Digilent.
-
-A comparison between the two FPGAs themselves can be seen in \autoref{tab:fpga-comparison}, a comparison between the peripherals on the development boards in \autoref{tab:devboard-comparison}.
-
-\begin{table}[h]
-\centering
-\begin{tabular}{l|r|r}
-\toprule
-               & Altera EP3C16 & Xilinx XC7A35T \\
-\midrule
-Logic Elements & 15000 & 33280 \\
-Multipliers    &    56 &    90 \\
-Block RAM (kb) &   504 &  1800 \\
-PLLs           &     4 &     5 \\
-Global clocks  &    20 &    32 \\
-\bottomrule
-\end{tabular}
-\caption{Comparison between Altera and Xilinx FPGAs}
-\label{tab:fpga-comparison}
-\end{table}
-
-\begin{table}[h]
-\centering
-\begin{tabular}{l|r|r}
-\toprule
-         & Terasic DE0 & Digilent Arty A7-35T \\
-\midrule
-Switches &           10 & 4 \\
-Buttons  &            3 & 4 \\
-LEDs     & 10 + 4x 7-segment & 4 + 3 RGB \\
-GPIOs    &        2x 36 & 4x PMOD + chipKIT \\
-Memory   &    8MB SDRAM & 256MB DDR3L \\
-Others   & SD card, VGA & Ethernet \\
-\bottomrule
-\end{tabular}
-\caption{Comparison between the peripherals on Terasic and Digilent FPGA development boards}
-\label{tab:devboard-comparison}
-\end{table}
-
-While the Digilent board offers fewer IO options, the DDR3 memory can be interfaced using Free memory cores and allows for much larger programs to be loaded, possibly even a full operating system. The missing VGA port has been substituted by an HDMI-compatible DVI interface that is accessible through one of the high-speed PMOD connectors.
-
-\subsection{Tooling}
-
-FPGA design is done using a Hardware Description Language (HDL). The two most well-known HDLs are Verilog and VHDL (VHSIC (Very high speed integrated circuit) HDL). As part of our studies at HTL, we exclusively worked with VHDL. For this reason, and because VHDL offers a strong type system~\cite{vhdl-types}, it was selected as the language of choice for the project.
-
-To refresh the reader's memory on the VHDL language, and as a quick guide for the tools involved in this project, see Appendix~\ref{app:vhdl-intro}.
-
-\subsubsection{Vendor Tools}
-
-The conventional way to work with FPGA designs is to use the FPGA vendor's development solution for simulation, synthesis and place-and-route. All of these tools are proprietary software specialized to a certain FPGA manufacturer, so a change of hardware also requires changing to a completely different software solution.
-
-Vendor tools are usually free-of-charge for basic usage, but this also means there is no guaranteed support. During the development of this project, several bugs and missing features were found in vendor tools that required workarounds.
-
-\subsubsection{Free Software Tools}
-
-A somewhat recent development is the creation of Free Software\footnotemark{} FPGA toolchains. A breakthrough was achieved by Claire (formerly Clifford) Wolf in 2013 with yosys~\cite{yosys-paper, yosys}, a feature-complete Verilog synthesis suite for Lattice's \texttt{iCE40} FPGA series.
-    \footnotetext{``Free Software'' refers to software that grants its user the freedom to share, study and modify it - see \url{https://www.fsf.org/about/what-is-free-software}.}
-Since then, both yosys and place-and-route tools like nextpnr~\cite{nextpnr} have matured, however Lattice's iCE40 and ECP5 remained the only supported FPGA architectures for place-and-route.
-
-Thus, two obstacles remained for Free toolchains to be viable for this project: synthesizing \emph{from} VHDL code and synthesizing \emph{to} Artix-7 FPGAs. During the development of the project, both of these were solved: Tristan Gingold released ghdlsynth-beta~\cite{ghdlsynth-beta}, a bridge between GHDL~\cite{ghdl} and yosys allowing VHDL to be synthesized just the same as Verilog, and Dave Shah added Xilinx support to nextpnr~\cite{nextpnr-xilinx}. The latter was preceded by many months of volunteer work reverse-engineering the Xilinx bitstream format as part of \textit{Project X-Ray}~\cite{prjxray}.
-
-With these two pieces in place, the project was switched over to a completely Free toolchain, removing any depencies on vendor tools:
-
-\begin{itemize}
- \item yosys, with ghdl as a frontend for processing VHDL and ghdlsynth as a bridge between them, is used to synthesize the design
- \item nextpnr-xilinx, together with the Project X-Ray database, is used for place-and-route
- \item tools from Project X-Ray are used to convert the routed design to a bitstream
- \item openFPGALoader is used to transfer the bitstream to the FPGA via JTAG
-\end{itemize}
-
 \section{SoC Peripherals}
 
 The complete FPGA design consists not only of the CPU core, but a number of components that allow it to operate as well as to communicate with the outside environment. They are connected to the core using a shared 32-bit bus.